From bd99158833bcec8442979f8bbab339dea4e18cf6 Mon Sep 17 00:00:00 2001 From: Tomasz Wlostowski Date: Thu, 12 Dec 2019 17:33:18 +0100 Subject: [PATCH] syn: svec7 XDC & synthesis files --- hdl/syn/common/svec7/Manifest.py | 4 + hdl/syn/common/svec7/ddr.xdc | 706 ++++++++++++++++++++++++++ hdl/syn/common/svec7/svec7.xdc | 717 +++++++++++++++++++++++++++ hdl/syn/svec7_test/buildinfo_pkg.vhd | 13 + 4 files changed, 1440 insertions(+) create mode 100644 hdl/syn/common/svec7/Manifest.py create mode 100644 hdl/syn/common/svec7/ddr.xdc create mode 100644 hdl/syn/common/svec7/svec7.xdc create mode 100644 hdl/syn/svec7_test/buildinfo_pkg.vhd diff --git a/hdl/syn/common/svec7/Manifest.py b/hdl/syn/common/svec7/Manifest.py new file mode 100644 index 0000000..161125b --- /dev/null +++ b/hdl/syn/common/svec7/Manifest.py @@ -0,0 +1,4 @@ +# User should define the variable svec_base_ucf + +files = [ "svec7.xdc", "ddr.xdc" ] + diff --git a/hdl/syn/common/svec7/ddr.xdc b/hdl/syn/common/svec7/ddr.xdc new file mode 100644 index 0000000..24879bf --- /dev/null +++ b/hdl/syn/common/svec7/ddr.xdc @@ -0,0 +1,706 @@ +################################################################################################## +## +## Xilinx, Inc. 2010 www.xilinx.com +## Wed Dec 11 19:18:42 2019 +## Generated by MIG Version 4.1 +## +################################################################################################## +## File name : svec7_ddr_controller_mig.xdc +## Details : Constraints file +## FPGA Family: KINTEX7 +## FPGA Part: XC7K160T-FBG676 +## Speedgrade: -2 +## Design Entry: VERILOG +## Frequency: 533.333 MHz +## Time Period: 1875 ps +################################################################################################## + +################################################################################################## +## Controller 0 +## Memory Device: DDR3_SDRAM->SODIMMs->svec-custom3 +## Data Width: 64 +## Time Period: 1875 +## Data Mask: 1 +################################################################################################## + +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_n[*]} ] +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_p[*]} ] + +#create_clock -period 5 [get_ports sys_clk_i] + +#create_clock -period 5 [get_ports clk_ref_i] + +############## NET - IOSTANDARD ################## + + +# PadFunction: IO_L1N_T0_34 +set_property SLEW FAST [get_ports {ddr3_dq[0]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[0]}] +set_property PACKAGE_PIN U5 [get_ports {ddr3_dq[0]}] + +# PadFunction: IO_L2P_T0_34 +set_property SLEW FAST [get_ports {ddr3_dq[1]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[1]}] +set_property PACKAGE_PIN U2 [get_ports {ddr3_dq[1]}] + +# PadFunction: IO_L2N_T0_34 +set_property SLEW FAST [get_ports {ddr3_dq[2]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[2]}] +set_property PACKAGE_PIN U1 [get_ports {ddr3_dq[2]}] + +# PadFunction: IO_L4P_T0_34 +set_property SLEW FAST [get_ports {ddr3_dq[3]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[3]}] +set_property PACKAGE_PIN V3 [get_ports {ddr3_dq[3]}] + +# PadFunction: IO_L4N_T0_34 +set_property SLEW FAST [get_ports {ddr3_dq[4]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[4]}] +set_property PACKAGE_PIN W3 [get_ports {ddr3_dq[4]}] + +# PadFunction: IO_L5P_T0_34 +set_property SLEW FAST [get_ports {ddr3_dq[5]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[5]}] +set_property PACKAGE_PIN U7 [get_ports {ddr3_dq[5]}] + +# PadFunction: IO_L5N_T0_34 +set_property SLEW FAST [get_ports {ddr3_dq[6]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[6]}] +set_property PACKAGE_PIN V6 [get_ports {ddr3_dq[6]}] + +# PadFunction: IO_L6P_T0_34 +set_property SLEW FAST [get_ports {ddr3_dq[7]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[7]}] +set_property PACKAGE_PIN V4 [get_ports {ddr3_dq[7]}] + +# PadFunction: IO_L7N_T1_34 +set_property SLEW FAST [get_ports {ddr3_dq[8]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[8]}] +set_property PACKAGE_PIN Y2 [get_ports {ddr3_dq[8]}] + +# PadFunction: IO_L8P_T1_34 +set_property SLEW FAST [get_ports {ddr3_dq[9]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[9]}] +set_property PACKAGE_PIN V2 [get_ports {ddr3_dq[9]}] + +# PadFunction: IO_L8N_T1_34 +set_property SLEW FAST [get_ports {ddr3_dq[10]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[10]}] +set_property PACKAGE_PIN V1 [get_ports {ddr3_dq[10]}] + +# PadFunction: IO_L10P_T1_34 +set_property SLEW FAST [get_ports {ddr3_dq[11]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[11]}] +set_property PACKAGE_PIN W1 [get_ports {ddr3_dq[11]}] + +# PadFunction: IO_L10N_T1_34 +set_property SLEW FAST [get_ports {ddr3_dq[12]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[12]}] +set_property PACKAGE_PIN Y1 [get_ports {ddr3_dq[12]}] + +# PadFunction: IO_L11P_T1_SRCC_34 +set_property SLEW FAST [get_ports {ddr3_dq[13]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[13]}] +set_property PACKAGE_PIN AB2 [get_ports {ddr3_dq[13]}] + +# PadFunction: IO_L11N_T1_SRCC_34 +set_property SLEW FAST [get_ports {ddr3_dq[14]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[14]}] +set_property PACKAGE_PIN AC2 [get_ports {ddr3_dq[14]}] + +# PadFunction: IO_L12P_T1_MRCC_34 +set_property SLEW FAST [get_ports {ddr3_dq[15]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[15]}] +set_property PACKAGE_PIN AA3 [get_ports {ddr3_dq[15]}] + +# PadFunction: IO_L13P_T2_MRCC_34 +set_property SLEW FAST [get_ports {ddr3_dq[16]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[16]}] +set_property PACKAGE_PIN AA4 [get_ports {ddr3_dq[16]}] + +# PadFunction: IO_L13N_T2_MRCC_34 +set_property SLEW FAST [get_ports {ddr3_dq[17]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[17]}] +set_property PACKAGE_PIN AB4 [get_ports {ddr3_dq[17]}] + +# PadFunction: IO_L14P_T2_SRCC_34 +set_property SLEW FAST [get_ports {ddr3_dq[18]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[18]}] +set_property PACKAGE_PIN AC4 [get_ports {ddr3_dq[18]}] + +# PadFunction: IO_L14N_T2_SRCC_34 +set_property SLEW FAST [get_ports {ddr3_dq[19]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[19]}] +set_property PACKAGE_PIN AC3 [get_ports {ddr3_dq[19]}] + +# PadFunction: IO_L16N_T2_34 +set_property SLEW FAST [get_ports {ddr3_dq[20]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[20]}] +set_property PACKAGE_PIN AC6 [get_ports {ddr3_dq[20]}] + +# PadFunction: IO_L17P_T2_34 +set_property SLEW FAST [get_ports {ddr3_dq[21]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[21]}] +set_property PACKAGE_PIN Y6 [get_ports {ddr3_dq[21]}] + +# PadFunction: IO_L17N_T2_34 +set_property SLEW FAST [get_ports {ddr3_dq[22]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[22]}] +set_property PACKAGE_PIN Y5 [get_ports {ddr3_dq[22]}] + +# PadFunction: IO_L18P_T2_34 +set_property SLEW FAST [get_ports {ddr3_dq[23]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[23]}] +set_property PACKAGE_PIN AD6 [get_ports {ddr3_dq[23]}] + +# PadFunction: IO_L20P_T3_34 +set_property SLEW FAST [get_ports {ddr3_dq[24]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[24]}] +set_property PACKAGE_PIN AD1 [get_ports {ddr3_dq[24]}] + +# PadFunction: IO_L20N_T3_34 +set_property SLEW FAST [get_ports {ddr3_dq[25]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[25]}] +set_property PACKAGE_PIN AE1 [get_ports {ddr3_dq[25]}] + +# PadFunction: IO_L22P_T3_34 +set_property SLEW FAST [get_ports {ddr3_dq[26]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[26]}] +set_property PACKAGE_PIN AE3 [get_ports {ddr3_dq[26]}] + +# PadFunction: IO_L22N_T3_34 +set_property SLEW FAST [get_ports {ddr3_dq[27]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[27]}] +set_property PACKAGE_PIN AE2 [get_ports {ddr3_dq[27]}] + +# PadFunction: IO_L23P_T3_34 +set_property SLEW FAST [get_ports {ddr3_dq[28]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[28]}] +set_property PACKAGE_PIN AE6 [get_ports {ddr3_dq[28]}] + +# PadFunction: IO_L23N_T3_34 +set_property SLEW FAST [get_ports {ddr3_dq[29]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[29]}] +set_property PACKAGE_PIN AE5 [get_ports {ddr3_dq[29]}] + +# PadFunction: IO_L24P_T3_34 +set_property SLEW FAST [get_ports {ddr3_dq[30]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[30]}] +set_property PACKAGE_PIN AF3 [get_ports {ddr3_dq[30]}] + +# PadFunction: IO_L24N_T3_34 +set_property SLEW FAST [get_ports {ddr3_dq[31]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[31]}] +set_property PACKAGE_PIN AF2 [get_ports {ddr3_dq[31]}] + +# PadFunction: IO_L1N_T0_32 +set_property SLEW FAST [get_ports {ddr3_dq[32]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[32]}] +set_property PACKAGE_PIN AF17 [get_ports {ddr3_dq[32]}] + +# PadFunction: IO_L2P_T0_32 +set_property SLEW FAST [get_ports {ddr3_dq[33]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[33]}] +set_property PACKAGE_PIN AF14 [get_ports {ddr3_dq[33]}] + +# PadFunction: IO_L2N_T0_32 +set_property SLEW FAST [get_ports {ddr3_dq[34]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[34]}] +set_property PACKAGE_PIN AF15 [get_ports {ddr3_dq[34]}] + +# PadFunction: IO_L4P_T0_32 +set_property SLEW FAST [get_ports {ddr3_dq[35]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[35]}] +set_property PACKAGE_PIN AD15 [get_ports {ddr3_dq[35]}] + +# PadFunction: IO_L4N_T0_32 +set_property SLEW FAST [get_ports {ddr3_dq[36]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[36]}] +set_property PACKAGE_PIN AE15 [get_ports {ddr3_dq[36]}] + +# PadFunction: IO_L5P_T0_32 +set_property SLEW FAST [get_ports {ddr3_dq[37]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[37]}] +set_property PACKAGE_PIN AF19 [get_ports {ddr3_dq[37]}] + +# PadFunction: IO_L5N_T0_32 +set_property SLEW FAST [get_ports {ddr3_dq[38]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[38]}] +set_property PACKAGE_PIN AF20 [get_ports {ddr3_dq[38]}] + +# PadFunction: IO_L6P_T0_32 +set_property SLEW FAST [get_ports {ddr3_dq[39]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[39]}] +set_property PACKAGE_PIN AD16 [get_ports {ddr3_dq[39]}] + +# PadFunction: IO_L7N_T1_32 +set_property SLEW FAST [get_ports {ddr3_dq[40]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[40]}] +set_property PACKAGE_PIN AA15 [get_ports {ddr3_dq[40]}] + +# PadFunction: IO_L8P_T1_32 +set_property SLEW FAST [get_ports {ddr3_dq[41]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[41]}] +set_property PACKAGE_PIN AC14 [get_ports {ddr3_dq[41]}] + +# PadFunction: IO_L8N_T1_32 +set_property SLEW FAST [get_ports {ddr3_dq[42]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[42]}] +set_property PACKAGE_PIN AD14 [get_ports {ddr3_dq[42]}] + +# PadFunction: IO_L10P_T1_32 +set_property SLEW FAST [get_ports {ddr3_dq[43]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[43]}] +set_property PACKAGE_PIN AB14 [get_ports {ddr3_dq[43]}] + +# PadFunction: IO_L10N_T1_32 +set_property SLEW FAST [get_ports {ddr3_dq[44]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[44]}] +set_property PACKAGE_PIN AB15 [get_ports {ddr3_dq[44]}] + +# PadFunction: IO_L11P_T1_SRCC_32 +set_property SLEW FAST [get_ports {ddr3_dq[45]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[45]}] +set_property PACKAGE_PIN AA17 [get_ports {ddr3_dq[45]}] + +# PadFunction: IO_L11N_T1_SRCC_32 +set_property SLEW FAST [get_ports {ddr3_dq[46]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[46]}] +set_property PACKAGE_PIN AA18 [get_ports {ddr3_dq[46]}] + +# PadFunction: IO_L12P_T1_MRCC_32 +set_property SLEW FAST [get_ports {ddr3_dq[47]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[47]}] +set_property PACKAGE_PIN AB16 [get_ports {ddr3_dq[47]}] + +# PadFunction: IO_L13P_T2_MRCC_32 +set_property SLEW FAST [get_ports {ddr3_dq[48]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[48]}] +set_property PACKAGE_PIN AC18 [get_ports {ddr3_dq[48]}] + +# PadFunction: IO_L13N_T2_MRCC_32 +set_property SLEW FAST [get_ports {ddr3_dq[49]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[49]}] +set_property PACKAGE_PIN AD18 [get_ports {ddr3_dq[49]}] + +# PadFunction: IO_L14P_T2_SRCC_32 +set_property SLEW FAST [get_ports {ddr3_dq[50]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[50]}] +set_property PACKAGE_PIN AB17 [get_ports {ddr3_dq[50]}] + +# PadFunction: IO_L14N_T2_SRCC_32 +set_property SLEW FAST [get_ports {ddr3_dq[51]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[51]}] +set_property PACKAGE_PIN AC17 [get_ports {ddr3_dq[51]}] + +# PadFunction: IO_L16N_T2_32 +set_property SLEW FAST [get_ports {ddr3_dq[52]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[52]}] +set_property PACKAGE_PIN AA20 [get_ports {ddr3_dq[52]}] + +# PadFunction: IO_L17P_T2_32 +set_property SLEW FAST [get_ports {ddr3_dq[53]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[53]}] +set_property PACKAGE_PIN AC19 [get_ports {ddr3_dq[53]}] + +# PadFunction: IO_L17N_T2_32 +set_property SLEW FAST [get_ports {ddr3_dq[54]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[54]}] +set_property PACKAGE_PIN AD19 [get_ports {ddr3_dq[54]}] + +# PadFunction: IO_L18P_T2_32 +set_property SLEW FAST [get_ports {ddr3_dq[55]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[55]}] +set_property PACKAGE_PIN AB19 [get_ports {ddr3_dq[55]}] + +# PadFunction: IO_L20P_T3_32 +set_property SLEW FAST [get_ports {ddr3_dq[56]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[56]}] +set_property PACKAGE_PIN V16 [get_ports {ddr3_dq[56]}] + +# PadFunction: IO_L20N_T3_32 +set_property SLEW FAST [get_ports {ddr3_dq[57]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[57]}] +set_property PACKAGE_PIN V17 [get_ports {ddr3_dq[57]}] + +# PadFunction: IO_L22P_T3_32 +set_property SLEW FAST [get_ports {ddr3_dq[58]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[58]}] +set_property PACKAGE_PIN W15 [get_ports {ddr3_dq[58]}] + +# PadFunction: IO_L22N_T3_32 +set_property SLEW FAST [get_ports {ddr3_dq[59]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[59]}] +set_property PACKAGE_PIN W16 [get_ports {ddr3_dq[59]}] + +# PadFunction: IO_L23P_T3_32 +set_property SLEW FAST [get_ports {ddr3_dq[60]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[60]}] +set_property PACKAGE_PIN V18 [get_ports {ddr3_dq[60]}] + +# PadFunction: IO_L23N_T3_32 +set_property SLEW FAST [get_ports {ddr3_dq[61]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[61]}] +set_property PACKAGE_PIN V19 [get_ports {ddr3_dq[61]}] + +# PadFunction: IO_L24P_T3_32 +set_property SLEW FAST [get_ports {ddr3_dq[62]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[62]}] +set_property PACKAGE_PIN V14 [get_ports {ddr3_dq[62]}] + +# PadFunction: IO_L24N_T3_32 +set_property SLEW FAST [get_ports {ddr3_dq[63]}] +set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[63]}] +set_property PACKAGE_PIN W14 [get_ports {ddr3_dq[63]}] + +# PadFunction: IO_L14P_T2_SRCC_33 +set_property SLEW FAST [get_ports {ddr3_addr[15]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[15]}] +set_property PACKAGE_PIN AA10 [get_ports {ddr3_addr[15]}] + +# PadFunction: IO_L13N_T2_MRCC_33 +set_property SLEW FAST [get_ports {ddr3_addr[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}] +set_property PACKAGE_PIN AC11 [get_ports {ddr3_addr[14]}] + +# PadFunction: IO_L1P_T0_33 +set_property SLEW FAST [get_ports {ddr3_addr[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}] +set_property PACKAGE_PIN V11 [get_ports {ddr3_addr[13]}] + +# PadFunction: IO_L1N_T0_33 +set_property SLEW FAST [get_ports {ddr3_addr[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}] +set_property PACKAGE_PIN W11 [get_ports {ddr3_addr[12]}] + +# PadFunction: IO_L2P_T0_33 +set_property SLEW FAST [get_ports {ddr3_addr[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}] +set_property PACKAGE_PIN V8 [get_ports {ddr3_addr[11]}] + +# PadFunction: IO_L2N_T0_33 +set_property SLEW FAST [get_ports {ddr3_addr[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}] +set_property PACKAGE_PIN V7 [get_ports {ddr3_addr[10]}] + +# PadFunction: IO_L4P_T0_33 +set_property SLEW FAST [get_ports {ddr3_addr[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}] +set_property PACKAGE_PIN Y8 [get_ports {ddr3_addr[9]}] + +# PadFunction: IO_L4N_T0_33 +set_property SLEW FAST [get_ports {ddr3_addr[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}] +set_property PACKAGE_PIN Y7 [get_ports {ddr3_addr[8]}] + +# PadFunction: IO_L5P_T0_33 +set_property SLEW FAST [get_ports {ddr3_addr[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}] +set_property PACKAGE_PIN Y11 [get_ports {ddr3_addr[7]}] + +# PadFunction: IO_L5N_T0_33 +set_property SLEW FAST [get_ports {ddr3_addr[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}] +set_property PACKAGE_PIN Y10 [get_ports {ddr3_addr[6]}] + +# PadFunction: IO_L6P_T0_33 +set_property SLEW FAST [get_ports {ddr3_addr[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}] +set_property PACKAGE_PIN V9 [get_ports {ddr3_addr[5]}] + +# PadFunction: IO_L13P_T2_MRCC_33 +set_property SLEW FAST [get_ports {ddr3_addr[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}] +set_property PACKAGE_PIN AB11 [get_ports {ddr3_addr[4]}] + +# PadFunction: IO_L7P_T1_33 +set_property SLEW FAST [get_ports {ddr3_addr[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}] +set_property PACKAGE_PIN AE7 [get_ports {ddr3_addr[3]}] + +# PadFunction: IO_L7N_T1_33 +set_property SLEW FAST [get_ports {ddr3_addr[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}] +set_property PACKAGE_PIN AF7 [get_ports {ddr3_addr[2]}] + +# PadFunction: IO_L8P_T1_33 +set_property SLEW FAST [get_ports {ddr3_addr[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}] +set_property PACKAGE_PIN AA8 [get_ports {ddr3_addr[1]}] + +# PadFunction: IO_L8N_T1_33 +set_property SLEW FAST [get_ports {ddr3_addr[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}] +set_property PACKAGE_PIN AA7 [get_ports {ddr3_addr[0]}] + +# PadFunction: IO_L9P_T1_DQS_33 +set_property SLEW FAST [get_ports {ddr3_ba[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}] +set_property PACKAGE_PIN AC8 [get_ports {ddr3_ba[2]}] + +# PadFunction: IO_L9N_T1_DQS_33 +set_property SLEW FAST [get_ports {ddr3_ba[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}] +set_property PACKAGE_PIN AD8 [get_ports {ddr3_ba[1]}] + +# PadFunction: IO_L10P_T1_33 +set_property SLEW FAST [get_ports {ddr3_ba[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}] +set_property PACKAGE_PIN AB7 [get_ports {ddr3_ba[0]}] + +# PadFunction: IO_L10N_T1_33 +set_property SLEW FAST [get_ports {ddr3_ras_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}] +set_property PACKAGE_PIN AC7 [get_ports {ddr3_ras_n}] + +# PadFunction: IO_L11P_T1_SRCC_33 +set_property SLEW FAST [get_ports {ddr3_cas_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}] +set_property PACKAGE_PIN AA9 [get_ports {ddr3_cas_n}] + +# PadFunction: IO_L11N_T1_SRCC_33 +set_property SLEW FAST [get_ports {ddr3_we_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}] +set_property PACKAGE_PIN AB9 [get_ports {ddr3_we_n}] + +# PadFunction: IO_L12N_T1_MRCC_34 +set_property SLEW FAST [get_ports {ddr3_reset_n}] +set_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}] +set_property PACKAGE_PIN AA2 [get_ports {ddr3_reset_n}] + +# PadFunction: IO_L15P_T2_DQS_33 +set_property SLEW FAST [get_ports {ddr3_cke[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}] +set_property PACKAGE_PIN AB12 [get_ports {ddr3_cke[0]}] + +# PadFunction: IO_L15N_T2_DQS_33 +set_property SLEW FAST [get_ports {ddr3_odt[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}] +set_property PACKAGE_PIN AC12 [get_ports {ddr3_odt[0]}] + +# PadFunction: IO_L12P_T1_MRCC_33 +set_property SLEW FAST [get_ports {ddr3_cs_n[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n[0]}] +set_property PACKAGE_PIN AC9 [get_ports {ddr3_cs_n[0]}] + +# PadFunction: IO_L1P_T0_34 +set_property SLEW FAST [get_ports {ddr3_dm[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}] +set_property PACKAGE_PIN U6 [get_ports {ddr3_dm[0]}] + +# PadFunction: IO_L7P_T1_34 +set_property SLEW FAST [get_ports {ddr3_dm[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}] +set_property PACKAGE_PIN Y3 [get_ports {ddr3_dm[1]}] + +# PadFunction: IO_L16P_T2_34 +set_property SLEW FAST [get_ports {ddr3_dm[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}] +set_property PACKAGE_PIN AB6 [get_ports {ddr3_dm[2]}] + +# PadFunction: IO_L19P_T3_34 +set_property SLEW FAST [get_ports {ddr3_dm[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}] +set_property PACKAGE_PIN AD4 [get_ports {ddr3_dm[3]}] + +# PadFunction: IO_L1P_T0_32 +set_property SLEW FAST [get_ports {ddr3_dm[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[4]}] +set_property PACKAGE_PIN AE17 [get_ports {ddr3_dm[4]}] + +# PadFunction: IO_L7P_T1_32 +set_property SLEW FAST [get_ports {ddr3_dm[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[5]}] +set_property PACKAGE_PIN AA14 [get_ports {ddr3_dm[5]}] + +# PadFunction: IO_L16P_T2_32 +set_property SLEW FAST [get_ports {ddr3_dm[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[6]}] +set_property PACKAGE_PIN AA19 [get_ports {ddr3_dm[6]}] + +# PadFunction: IO_L19P_T3_32 +set_property SLEW FAST [get_ports {ddr3_dm[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[7]}] +set_property PACKAGE_PIN Y17 [get_ports {ddr3_dm[7]}] + +# PadFunction: IO_L3P_T0_DQS_34 +set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[0]}] +set_property PACKAGE_PIN W6 [get_ports {ddr3_dqs_p[0]}] + +# PadFunction: IO_L3N_T0_DQS_34 +set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[0]}] +set_property PACKAGE_PIN W5 [get_ports {ddr3_dqs_n[0]}] + +# PadFunction: IO_L9P_T1_DQS_34 +set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[1]}] +set_property PACKAGE_PIN AB1 [get_ports {ddr3_dqs_p[1]}] + +# PadFunction: IO_L9N_T1_DQS_34 +set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[1]}] +set_property PACKAGE_PIN AC1 [get_ports {ddr3_dqs_n[1]}] + +# PadFunction: IO_L15P_T2_DQS_34 +set_property SLEW FAST [get_ports {ddr3_dqs_p[2]}] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[2]}] +set_property PACKAGE_PIN AA5 [get_ports {ddr3_dqs_p[2]}] + +# PadFunction: IO_L15N_T2_DQS_34 +set_property SLEW FAST [get_ports {ddr3_dqs_n[2]}] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[2]}] +set_property PACKAGE_PIN AB5 [get_ports {ddr3_dqs_n[2]}] + +# PadFunction: IO_L21P_T3_DQS_34 +set_property SLEW FAST [get_ports {ddr3_dqs_p[3]}] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[3]}] +set_property PACKAGE_PIN AF5 [get_ports {ddr3_dqs_p[3]}] + +# PadFunction: IO_L21N_T3_DQS_34 +set_property SLEW FAST [get_ports {ddr3_dqs_n[3]}] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[3]}] +set_property PACKAGE_PIN AF4 [get_ports {ddr3_dqs_n[3]}] + +# PadFunction: IO_L3P_T0_DQS_32 +set_property SLEW FAST [get_ports {ddr3_dqs_p[4]}] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[4]}] +set_property PACKAGE_PIN AE18 [get_ports {ddr3_dqs_p[4]}] + +# PadFunction: IO_L3N_T0_DQS_32 +set_property SLEW FAST [get_ports {ddr3_dqs_n[4]}] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[4]}] +set_property PACKAGE_PIN AF18 [get_ports {ddr3_dqs_n[4]}] + +# PadFunction: IO_L9P_T1_DQS_32 +set_property SLEW FAST [get_ports {ddr3_dqs_p[5]}] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[5]}] +set_property PACKAGE_PIN Y15 [get_ports {ddr3_dqs_p[5]}] + +# PadFunction: IO_L9N_T1_DQS_32 +set_property SLEW FAST [get_ports {ddr3_dqs_n[5]}] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[5]}] +set_property PACKAGE_PIN Y16 [get_ports {ddr3_dqs_n[5]}] + +# PadFunction: IO_L15P_T2_DQS_32 +set_property SLEW FAST [get_ports {ddr3_dqs_p[6]}] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[6]}] +set_property PACKAGE_PIN AD20 [get_ports {ddr3_dqs_p[6]}] + +# PadFunction: IO_L15N_T2_DQS_32 +set_property SLEW FAST [get_ports {ddr3_dqs_n[6]}] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[6]}] +set_property PACKAGE_PIN AE20 [get_ports {ddr3_dqs_n[6]}] + +# PadFunction: IO_L21P_T3_DQS_32 +set_property SLEW FAST [get_ports {ddr3_dqs_p[7]}] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[7]}] +set_property PACKAGE_PIN W18 [get_ports {ddr3_dqs_p[7]}] + +# PadFunction: IO_L21N_T3_DQS_32 +set_property SLEW FAST [get_ports {ddr3_dqs_n[7]}] +set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[7]}] +set_property PACKAGE_PIN W19 [get_ports {ddr3_dqs_n[7]}] + +# PadFunction: IO_L3P_T0_DQS_33 +set_property SLEW FAST [get_ports {ddr3_ck_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}] +set_property PACKAGE_PIN W10 [get_ports {ddr3_ck_p[0]}] + +# PadFunction: IO_L3N_T0_DQS_33 +set_property SLEW FAST [get_ports {ddr3_ck_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}] +set_property PACKAGE_PIN W9 [get_ports {ddr3_ck_n[0]}] + + + +set_property LOC PHASER_OUT_PHY_X1Y3 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}] + +set_property LOC PHASER_IN_PHY_X1Y3 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}] +## set_property LOC PHASER_IN_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}] +## set_property LOC PHASER_IN_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}] +## set_property LOC PHASER_IN_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}] + + + +set_property LOC OUT_FIFO_X1Y3 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}] +set_property LOC OUT_FIFO_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] +set_property LOC OUT_FIFO_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] +set_property LOC OUT_FIFO_X1Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}] +set_property LOC OUT_FIFO_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}] +set_property LOC OUT_FIFO_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] +set_property LOC OUT_FIFO_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] +set_property LOC OUT_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}] +set_property LOC OUT_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] +set_property LOC OUT_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] +set_property LOC OUT_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}] + +set_property LOC IN_FIFO_X1Y3 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}] + +set_property LOC PHY_CONTROL_X1Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/phy_control_i}] +set_property LOC PHY_CONTROL_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i}] +set_property LOC PHY_CONTROL_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}] + +set_property LOC PHASER_REF_X1Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_ref_i}] +set_property LOC PHASER_REF_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i}] +set_property LOC PHASER_REF_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}] + +set_property LOC OLOGIC_X1Y43 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y31 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y19 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y143 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y131 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y119 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y107 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}] + +set_property LOC PLLE2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}] +set_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}] + + +set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \ + -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \ + -setup 6 + +set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \ + -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \ + -hold 5 + +set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]] + +set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start +set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start + +#set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20 +set_max_delay -to [get_pins -hier -include_replicated_objects -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[*]/D}] 20 +set_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5 +#set_false_path -through [get_pins -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst}] +set_false_path -through [get_nets -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst_i}] + +set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20 + \ No newline at end of file diff --git a/hdl/syn/common/svec7/svec7.xdc b/hdl/syn/common/svec7/svec7.xdc new file mode 100644 index 0000000..847b008 --- /dev/null +++ b/hdl/syn/common/svec7/svec7.xdc @@ -0,0 +1,717 @@ +# PadFunction: IO_L12P_T1_MRCC_14 +set_property PACKAGE_PIN F22 [get_ports {clk_20m_vcxo_i}] +set_property IOSTANDARD LVCMOS25 [get_ports {clk_20m_vcxo_i}] +# PadFunction: IO_L13P_T2_MRCC_14 +set_property PACKAGE_PIN G22 [get_ports {clk_125m_pllref_p_i}] +set_property IOSTANDARD LVDS_25 [get_ports {clk_125m_pllref_p_i}] +# PadFunction: IO_L13N_T2_MRCC_14 +set_property PACKAGE_PIN F23 [get_ports {clk_125m_pllref_n_i}] +set_property IOSTANDARD LVDS_25 [get_ports {clk_125m_pllref_n_i}] +# PadFunction: MGTREFCLK0N_115 +set_property PACKAGE_PIN H5 [get_ports {clk_125m_gtx_n_i}] +set_property IOSTANDARD LVCMOS33 [get_ports {clk_125m_gtx_n_i}] +# PadFunction: MGTREFCLK0P_115 +set_property PACKAGE_PIN H6 [get_ports {clk_125m_gtx_p_i}] +set_property IOSTANDARD LVCMOS33 [get_ports {clk_125m_gtx_p_i}] +# PadFunction: IO_L13P_T2_MRCC_16 +set_property PACKAGE_PIN C12 [get_ports {clk_fpga2_p_i}] +set_property IOSTANDARD LVDS_25 [get_ports {clk_fpga2_p_i}] +# PadFunction: IO_L13N_T2_MRCC_16 +set_property PACKAGE_PIN C11 [get_ports {clk_fpga2_n_i}] +set_property IOSTANDARD LVDS_25 [get_ports {clk_fpga2_n_i}] +# PadFunction: IO_L12P_T1_MRCC_16 +set_property PACKAGE_PIN E10 [get_ports {clk_si57x_p_i}] +set_property IOSTANDARD LVDS_25 [get_ports {clk_si57x_p_i}] +# PadFunction: IO_L12N_T1_MRCC_16 +set_property PACKAGE_PIN D10 [get_ports {clk_si57x_n_i}] +set_property IOSTANDARD LVDS_25 [get_ports {clk_si57x_n_i}] +# PadFunction: IO_L12P_T1_MRCC_12 +set_property PACKAGE_PIN Y23 [get_ports {fmc0_clk_m2c_p_i[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_clk_m2c_p_i[0]}] +# PadFunction: IO_L12N_T1_MRCC_12 +set_property PACKAGE_PIN AA24 [get_ports {fmc0_clk_m2c_n_i[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_clk_m2c_n_i[0]}] +# PadFunction: IO_L13P_T2_MRCC_12 +set_property PACKAGE_PIN Y22 [get_ports {fmc0_clk_m2c_p_i[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_clk_m2c_p_i[1]}] +# PadFunction: IO_L13N_T2_MRCC_12 +set_property PACKAGE_PIN AA22 [get_ports {fmc0_clk_m2c_n_i[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_clk_m2c_n_i[1]}] +# PadFunction: IO_L12P_T1_MRCC_13 +set_property PACKAGE_PIN N21 [get_ports {fmc1_clk_m2c_p_i[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_clk_m2c_p_i[0]}] +# PadFunction: IO_L12N_T1_MRCC_13 +set_property PACKAGE_PIN N22 [get_ports {fmc1_clk_m2c_n_i[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_clk_m2c_n_i[0]}] +# PadFunction: IO_L13P_T2_MRCC_13 +set_property PACKAGE_PIN R21 [get_ports {fmc1_clk_m2c_p_i[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_clk_m2c_p_i[1]}] +# PadFunction: IO_L13P_T2_MRCC_13 +set_property PACKAGE_PIN R21 [get_ports {fmc1_clk_m2c_n_i[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_clk_m2c_n_i[1]}] +# PadFunction: IO_L12P_T1_MRCC_AD5P_15 +set_property PACKAGE_PIN F17 [get_ports {fmc0_la_p_b[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[0]}] +# PadFunction: IO_L12N_T1_MRCC_AD5N_15 +set_property PACKAGE_PIN E17 [get_ports {fmc0_la_n_b[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[0]}] +# PadFunction: IO_L13P_T2_MRCC_15 +set_property PACKAGE_PIN E18 [get_ports {fmc1_la_p_b[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[0]}] +# PadFunction: IO_L13N_T2_MRCC_15 +set_property PACKAGE_PIN D18 [get_ports {fmc1_la_n_b[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[0]}] +# PadFunction: IO_L11P_T1_SRCC_12 +set_property PACKAGE_PIN AA23 [get_ports {fmc0_la_p_b[17]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[17]}] +# PadFunction: IO_L11N_T1_SRCC_12 +set_property PACKAGE_PIN AB24 [get_ports {fmc0_la_n_b[17]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[17]}] +# PadFunction: IO_L11P_T1_SRCC_13 +set_property PACKAGE_PIN P23 [get_ports {fmc1_la_p_b[17]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[17]}] +# PadFunction: IO_L11N_T1_SRCC_13 +set_property PACKAGE_PIN N23 [get_ports {fmc1_la_n_b[17]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[17]}] +# PadFunction: IO_L1P_T0_12 +set_property PACKAGE_PIN U22 [get_ports {fmc0_la_p_b[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[1]}] +# PadFunction: IO_L2P_T0_12 +set_property PACKAGE_PIN U24 [get_ports {fmc0_la_p_b[2]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[2]}] +# PadFunction: IO_L3P_T0_DQS_12 +set_property PACKAGE_PIN V23 [get_ports {fmc0_la_p_b[3]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[3]}] +# PadFunction: IO_L4P_T0_12 +set_property PACKAGE_PIN U26 [get_ports {fmc0_la_p_b[4]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[4]}] +# PadFunction: IO_L5P_T0_12 +set_property PACKAGE_PIN W25 [get_ports {fmc0_la_p_b[5]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[5]}] +# PadFunction: IO_L6P_T0_12 +set_property PACKAGE_PIN V21 [get_ports {fmc0_la_p_b[6]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[6]}] +# PadFunction: IO_L7P_T1_12 +set_property PACKAGE_PIN AA25 [get_ports {fmc0_la_p_b[7]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[7]}] +# PadFunction: IO_L8P_T1_12 +set_property PACKAGE_PIN W23 [get_ports {fmc0_la_p_b[8]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[8]}] +# PadFunction: IO_L9P_T1_DQS_12 +set_property PACKAGE_PIN AB26 [get_ports {fmc0_la_p_b[9]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[9]}] +# PadFunction: IO_L10P_T1_12 +set_property PACKAGE_PIN Y25 [get_ports {fmc0_la_p_b[10]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[10]}] +# PadFunction: IO_L14P_T2_SRCC_12 +set_property PACKAGE_PIN AC23 [get_ports {fmc0_la_p_b[11]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[11]}] +# PadFunction: IO_L15P_T2_DQS_12 +set_property PACKAGE_PIN W20 [get_ports {fmc0_la_p_b[12]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[12]}] +# PadFunction: IO_L16P_T2_12 +set_property PACKAGE_PIN AD23 [get_ports {fmc0_la_p_b[13]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[13]}] +# PadFunction: IO_L17P_T2_12 +set_property PACKAGE_PIN AB22 [get_ports {fmc0_la_p_b[14]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[14]}] +# PadFunction: IO_L18P_T2_12 +set_property PACKAGE_PIN AB21 [get_ports {fmc0_la_p_b[15]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[15]}] +# PadFunction: IO_L19P_T3_12 +set_property PACKAGE_PIN AD21 [get_ports {fmc0_la_p_b[16]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[16]}] +# PadFunction: IO_L1N_T0_12 +set_property PACKAGE_PIN V22 [get_ports {fmc0_la_n_b[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[1]}] +# PadFunction: IO_L2N_T0_12 +set_property PACKAGE_PIN U25 [get_ports {fmc0_la_n_b[2]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[2]}] +# PadFunction: IO_L3N_T0_DQS_12 +set_property PACKAGE_PIN V24 [get_ports {fmc0_la_n_b[3]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[3]}] +# PadFunction: IO_L4N_T0_12 +set_property PACKAGE_PIN V26 [get_ports {fmc0_la_n_b[4]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[4]}] +# PadFunction: IO_L5N_T0_12 +set_property PACKAGE_PIN W26 [get_ports {fmc0_la_n_b[5]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[5]}] +# PadFunction: IO_L6N_T0_VREF_12 +set_property PACKAGE_PIN W21 [get_ports {fmc0_la_n_b[6]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[6]}] +# PadFunction: IO_L7N_T1_12 +set_property PACKAGE_PIN AB25 [get_ports {fmc0_la_n_b[7]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[7]}] +# PadFunction: IO_L8N_T1_12 +set_property PACKAGE_PIN W24 [get_ports {fmc0_la_n_b[8]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[8]}] +# PadFunction: IO_L9N_T1_DQS_12 +set_property PACKAGE_PIN AC26 [get_ports {fmc0_la_n_b[9]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[9]}] +# PadFunction: IO_L10N_T1_12 +set_property PACKAGE_PIN Y26 [get_ports {fmc0_la_n_b[10]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[10]}] +# PadFunction: IO_L14N_T2_SRCC_12 +set_property PACKAGE_PIN AC24 [get_ports {fmc0_la_n_b[11]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[11]}] +# PadFunction: IO_L15N_T2_DQS_12 +set_property PACKAGE_PIN Y21 [get_ports {fmc0_la_n_b[12]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[12]}] +# PadFunction: IO_L16N_T2_12 +set_property PACKAGE_PIN AD24 [get_ports {fmc0_la_n_b[13]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[13]}] +# PadFunction: IO_L17N_T2_12 +set_property PACKAGE_PIN AC22 [get_ports {fmc0_la_n_b[14]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[14]}] +# PadFunction: IO_L18N_T2_12 +set_property PACKAGE_PIN AC21 [get_ports {fmc0_la_n_b[15]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[15]}] +# PadFunction: IO_L19N_T3_VREF_12 +set_property PACKAGE_PIN AE21 [get_ports {fmc0_la_n_b[16]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_n_b[16]}] +# PadFunction: IO_L20P_T3_12 +set_property PACKAGE_PIN AF24 [get_ports {fmc1_la_p_b[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[1]}] +# PadFunction: IO_L21P_T3_DQS_12 +set_property PACKAGE_PIN AD26 [get_ports {fmc1_la_p_b[2]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[2]}] +# PadFunction: IO_L22P_T3_12 +set_property PACKAGE_PIN AE23 [get_ports {fmc1_la_p_b[3]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[3]}] +# PadFunction: IO_L23P_T3_12 +set_property PACKAGE_PIN AD25 [get_ports {fmc1_la_p_b[4]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[4]}] +# PadFunction: IO_L24P_T3_12 +set_property PACKAGE_PIN AE22 [get_ports {fmc1_la_p_b[5]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[5]}] +# PadFunction: IO_L1P_T0_13 +set_property PACKAGE_PIN K25 [get_ports {fmc1_la_p_b[6]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[6]}] +# PadFunction: IO_L2P_T0_13 +set_property PACKAGE_PIN R26 [get_ports {fmc1_la_p_b[7]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[7]}] +# PadFunction: IO_L3P_T0_DQS_13 +set_property PACKAGE_PIN M25 [get_ports {fmc1_la_p_b[8]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[8]}] +# PadFunction: IO_L4P_T0_13 +set_property PACKAGE_PIN P24 [get_ports {fmc1_la_p_b[9]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[9]}] +# PadFunction: IO_L5P_T0_13 +set_property PACKAGE_PIN N26 [get_ports {fmc1_la_p_b[10]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[10]}] +# PadFunction: IO_L6P_T0_13 +set_property PACKAGE_PIN R25 [get_ports {fmc1_la_p_b[11]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[11]}] +# PadFunction: IO_L7P_T1_13 +set_property PACKAGE_PIN N19 [get_ports {fmc1_la_p_b[12]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[12]}] +# PadFunction: IO_L8P_T1_13 +set_property PACKAGE_PIN M24 [get_ports {fmc1_la_p_b[13]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[13]}] +# PadFunction: IO_L9P_T1_DQS_13 +set_property PACKAGE_PIN P19 [get_ports {fmc1_la_p_b[14]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[14]}] +# PadFunction: IO_L10P_T1_13 +set_property PACKAGE_PIN M21 [get_ports {fmc1_la_p_b[15]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[15]}] +# PadFunction: IO_L14P_T2_SRCC_13 +set_property PACKAGE_PIN R22 [get_ports {fmc1_la_p_b[16]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[16]}] +# PadFunction: IO_L20N_T3_12 +set_property PACKAGE_PIN AF25 [get_ports {fmc1_la_n_b[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[1]}] +# PadFunction: IO_L21N_T3_DQS_12 +set_property PACKAGE_PIN AE26 [get_ports {fmc1_la_n_b[2]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[2]}] +# PadFunction: IO_L22N_T3_12 +set_property PACKAGE_PIN AF23 [get_ports {fmc1_la_n_b[3]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[3]}] +# PadFunction: IO_L23N_T3_12 +set_property PACKAGE_PIN AE25 [get_ports {fmc1_la_n_b[4]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[4]}] +# PadFunction: IO_L24N_T3_12 +set_property PACKAGE_PIN AF22 [get_ports {fmc1_la_n_b[5]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[5]}] +# PadFunction: IO_L1N_T0_13 +set_property PACKAGE_PIN K26 [get_ports {fmc1_la_n_b[6]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[6]}] +# PadFunction: IO_L2N_T0_13 +set_property PACKAGE_PIN P26 [get_ports {fmc1_la_n_b[7]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[7]}] +# PadFunction: IO_L3N_T0_DQS_13 +set_property PACKAGE_PIN L25 [get_ports {fmc1_la_n_b[8]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[8]}] +# PadFunction: IO_L4N_T0_13 +set_property PACKAGE_PIN N24 [get_ports {fmc1_la_n_b[9]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[9]}] +# PadFunction: IO_L5N_T0_13 +set_property PACKAGE_PIN M26 [get_ports {fmc1_la_n_b[10]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[10]}] +# PadFunction: IO_L6N_T0_VREF_13 +set_property PACKAGE_PIN P25 [get_ports {fmc1_la_n_b[11]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[11]}] +# PadFunction: IO_L7N_T1_13 +set_property PACKAGE_PIN M20 [get_ports {fmc1_la_n_b[12]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[12]}] +# PadFunction: IO_L8N_T1_13 +set_property PACKAGE_PIN L24 [get_ports {fmc1_la_n_b[13]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[13]}] +# PadFunction: IO_L9N_T1_DQS_13 +set_property PACKAGE_PIN P20 [get_ports {fmc1_la_n_b[14]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[14]}] +# PadFunction: IO_L10N_T1_13 +set_property PACKAGE_PIN M22 [get_ports {fmc1_la_n_b[15]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[15]}] +# PadFunction: IO_L14N_T2_SRCC_13 +set_property PACKAGE_PIN R23 [get_ports {fmc1_la_n_b[16]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_n_b[16]}] +# PadFunction: IO_L15P_T2_DQS_13 +set_property PACKAGE_PIN T24 [get_ports {fmc0_la_p_b[18]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[18]}] +# PadFunction: IO_L16P_T2_13 +set_property PACKAGE_PIN T20 [get_ports {fmc0_la_p_b[19]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[19]}] +# PadFunction: IO_L17P_T2_13 +set_property PACKAGE_PIN T22 [get_ports {fmc0_la_p_b[20]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[20]}] +# PadFunction: IO_L18P_T2_13 +set_property PACKAGE_PIN U19 [get_ports {fmc0_la_p_b[21]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[21]}] +# PadFunction: IO_L19P_T3_13 +set_property PACKAGE_PIN T18 [get_ports {fmc0_la_p_b[22]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[22]}] +# PadFunction: IO_L20P_T3_13 +set_property PACKAGE_PIN P16 [get_ports {fmc0_la_p_b[23]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[23]}] +# PadFunction: IO_L21P_T3_DQS_13 +set_property PACKAGE_PIN R16 [get_ports {fmc0_la_p_b[24]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[24]}] +# PadFunction: IO_L22P_T3_13 +set_property PACKAGE_PIN N18 [get_ports {fmc0_la_p_b[25]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[25]}] +# PadFunction: IO_L23P_T3_13 +set_property PACKAGE_PIN U17 [get_ports {fmc0_la_p_b[26]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[26]}] +# PadFunction: IO_L24P_T3_13 +set_property PACKAGE_PIN R18 [get_ports {fmc0_la_p_b[27]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[27]}] +# PadFunction: IO_L1P_T0_AD0P_15 +set_property PACKAGE_PIN C16 [get_ports {fmc0_la_p_b[28]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[28]}] +# PadFunction: IO_L2P_T0_AD8P_15 +set_property PACKAGE_PIN A18 [get_ports {fmc0_la_p_b[29]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[29]}] +# PadFunction: IO_L3P_T0_DQS_AD1P_15 +set_property PACKAGE_PIN B17 [get_ports {fmc0_la_p_b[30]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[30]}] +# PadFunction: IO_L4P_T0_AD9P_15 +set_property PACKAGE_PIN C19 [get_ports {fmc0_la_p_b[31]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[31]}] +# PadFunction: IO_L5P_T0_AD2P_15 +set_property PACKAGE_PIN C17 [get_ports {fmc0_la_p_b[32]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[32]}] +# PadFunction: IO_L6P_T0_15 +set_property PACKAGE_PIN D15 [get_ports {fmc0_la_p_b[33]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[33]}] +# PadFunction: IO_L7P_T1_AD10P_15 +set_property PACKAGE_PIN H16 [get_ports {fmc1_la_p_b[18]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[18]}] +# PadFunction: IO_L8P_T1_AD3P_15 +set_property PACKAGE_PIN G15 [get_ports {fmc1_la_p_b[19]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[19]}] +# PadFunction: IO_L9P_T1_DQS_AD11P_15 +set_property PACKAGE_PIN J15 [get_ports {fmc1_la_p_b[20]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[20]}] +# PadFunction: IO_L10P_T1_AD4P_15 +set_property PACKAGE_PIN E15 [get_ports {fmc1_la_p_b[21]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[21]}] +# PadFunction: IO_L11P_T1_SRCC_AD12P_15 +set_property PACKAGE_PIN G17 [get_ports {fmc1_la_p_b[22]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[22]}] +# PadFunction: IO_L14P_T2_SRCC_15 +set_property PACKAGE_PIN H17 [get_ports {fmc1_la_p_b[23]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[23]}] +# PadFunction: IO_L15P_T2_DQS_15 +set_property PACKAGE_PIN D19 [get_ports {fmc1_la_p_b[24]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[24]}] +# PadFunction: IO_L16P_T2_A28_15 +set_property PACKAGE_PIN G19 [get_ports {fmc1_la_p_b[25]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[25]}] +# PadFunction: IO_L17P_T2_A26_15 +set_property PACKAGE_PIN F19 [get_ports {fmc1_la_p_b[26]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[26]}] +# PadFunction: IO_L18P_T2_A24_15 +set_property PACKAGE_PIN H19 [get_ports {fmc1_la_p_b[27]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[27]}] +# PadFunction: IO_L19P_T3_A22_15 +set_property PACKAGE_PIN K20 [get_ports {fmc1_la_p_b[28]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[28]}] +# PadFunction: IO_L20P_T3_A20_15 +set_property PACKAGE_PIN J18 [get_ports {fmc1_la_p_b[29]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[29]}] +# PadFunction: IO_L21P_T3_DQS_15 +set_property PACKAGE_PIN L19 [get_ports {fmc1_la_p_b[30]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[30]}] +# PadFunction: IO_L22P_T3_A17_15 +set_property PACKAGE_PIN K16 [get_ports {fmc1_la_p_b[31]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[31]}] +# PadFunction: IO_L23P_T3_FOE_B_15 +set_property PACKAGE_PIN M17 [get_ports {fmc1_la_p_b[32]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[32]}] +# PadFunction: IO_L24P_T3_RS1_15 +set_property PACKAGE_PIN L17 [get_ports {fmc1_la_p_b[33]}] +set_property IOSTANDARD LVDS_25 [get_ports {fmc1_la_p_b[33]}] +# PadFunction: IO_0_14 +set_property PACKAGE_PIN K21 [get_ports {p2_b[0]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[0]}] +# PadFunction: IO_L2P_T0_D02_14 +set_property PACKAGE_PIN B22 [get_ports {p2_b[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[1]}] +# PadFunction: IO_L2N_T0_D03_14 +set_property PACKAGE_PIN A22 [get_ports {p2_b[2]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[2]}] +# PadFunction: IO_L3P_T0_DQS_PUDC_B_14 +set_property PACKAGE_PIN B25 [get_ports {p2_b[3]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[3]}] +# PadFunction: IO_L3N_T0_DQS_EMCCLK_14 +set_property PACKAGE_PIN B26 [get_ports {p2_b[4]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[4]}] +# PadFunction: IO_L4P_T0_D04_14 +set_property PACKAGE_PIN A23 [get_ports {p2_b[5]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[5]}] +# PadFunction: IO_L4N_T0_D05_14 +set_property PACKAGE_PIN A24 [get_ports {p2_b[6]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[6]}] +# PadFunction: IO_L5P_T0_D06_14 +set_property PACKAGE_PIN D26 [get_ports {p2_b[7]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[7]}] +# PadFunction: IO_L5N_T0_D07_14 +set_property PACKAGE_PIN C26 [get_ports {p2_b[8]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[8]}] +# PadFunction: IO_L7P_T1_D09_14 +set_property PACKAGE_PIN D21 [get_ports {p2_b[9]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[9]}] +# PadFunction: IO_L7N_T1_D10_14 +set_property PACKAGE_PIN C22 [get_ports {p2_b[10]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[10]}] +# PadFunction: IO_L8P_T1_D11_14 +set_property PACKAGE_PIN B20 [get_ports {p2_b[11]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[11]}] +# PadFunction: IO_L8N_T1_D12_14 +set_property PACKAGE_PIN A20 [get_ports {p2_b[12]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[12]}] +# PadFunction: IO_L9P_T1_DQS_14 +set_property PACKAGE_PIN E21 [get_ports {p2_b[13]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[13]}] +# PadFunction: IO_L9N_T1_DQS_D13_14 +set_property PACKAGE_PIN E22 [get_ports {p2_b[14]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[14]}] +# PadFunction: IO_L10P_T1_D14_14 +set_property PACKAGE_PIN C21 [get_ports {p2_b[15]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[15]}] +# PadFunction: IO_L10N_T1_D15_14 +set_property PACKAGE_PIN B21 [get_ports {p2_b[16]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[16]}] +# PadFunction: IO_L11P_T1_SRCC_14 +set_property PACKAGE_PIN D23 [get_ports {p2_b[17]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[17]}] +# PadFunction: IO_L11N_T1_SRCC_14 +set_property PACKAGE_PIN D24 [get_ports {p2_b[18]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[18]}] +# PadFunction: IO_L12N_T1_MRCC_14 +set_property PACKAGE_PIN E23 [get_ports {p2_b[19]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[19]}] +# PadFunction: IO_L14N_T2_SRCC_14 +set_property PACKAGE_PIN F24 [get_ports {p2_b[20]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[20]}] +# PadFunction: IO_L15P_T2_DQS_RDWR_B_14 +set_property PACKAGE_PIN E25 [get_ports {p2_b[21]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[21]}] +# PadFunction: IO_L15N_T2_DQS_DOUT_CSO_B_14 +set_property PACKAGE_PIN D25 [get_ports {p2_b[22]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[22]}] +# PadFunction: IO_L16P_T2_CSI_B_14 +set_property PACKAGE_PIN G25 [get_ports {p2_b[23]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[23]}] +# PadFunction: IO_L16N_T2_A15_D31_14 +set_property PACKAGE_PIN G26 [get_ports {p2_b[24]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[24]}] +# PadFunction: IO_L17P_T2_A14_D30_14 +set_property PACKAGE_PIN F25 [get_ports {p2_b[25]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[25]}] +# PadFunction: IO_L17N_T2_A13_D29_14 +set_property PACKAGE_PIN E26 [get_ports {p2_b[26]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[26]}] +# PadFunction: IO_L18P_T2_A12_D28_14 +set_property PACKAGE_PIN J26 [get_ports {p2_b[27]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[27]}] +# PadFunction: IO_L18N_T2_A11_D27_14 +set_property PACKAGE_PIN H26 [get_ports {p2_b[28]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[28]}] +# PadFunction: IO_L19P_T3_A10_D26_14 +set_property PACKAGE_PIN H21 [get_ports {p2_b[29]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[29]}] +# PadFunction: IO_L20P_T3_A08_D24_14 +set_property PACKAGE_PIN H23 [get_ports {p2_b[30]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[30]}] +# PadFunction: IO_L20N_T3_A07_D23_14 +set_property PACKAGE_PIN H24 [get_ports {p2_b[31]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[31]}] +# PadFunction: IO_L21P_T3_DQS_14 +set_property PACKAGE_PIN J21 [get_ports {p2_b[32]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[32]}] +# PadFunction: IO_L21N_T3_DQS_A06_D22_14 +set_property PACKAGE_PIN H22 [get_ports {p2_b[33]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[33]}] +# PadFunction: IO_L22P_T3_A05_D21_14 +set_property PACKAGE_PIN J24 [get_ports {p2_b[34]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[34]}] +# PadFunction: IO_L22N_T3_A04_D20_14 +set_property PACKAGE_PIN J25 [get_ports {p2_b[35]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[35]}] +# PadFunction: IO_L23P_T3_A03_D19_14 +set_property PACKAGE_PIN L22 [get_ports {p2_b[36]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[36]}] +# PadFunction: IO_L23N_T3_A02_D18_14 +set_property PACKAGE_PIN K22 [get_ports {p2_b[37]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[37]}] +# PadFunction: IO_L24P_T3_A01_D17_14 +set_property PACKAGE_PIN K23 [get_ports {p2_b[38]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[38]}] +# PadFunction: IO_L24N_T3_A00_D16_14 +set_property PACKAGE_PIN J23 [get_ports {p2_b[39]}] +set_property IOSTANDARD LVCMOS25 [get_ports {p2_b[39]}] +# PadFunction: IO_25_14 +set_property PACKAGE_PIN L23 [get_ports {rst_n_i}] +set_property IOSTANDARD LVCMOS25 [get_ports {rst_n_i}] +# PadFunction: IO_0_16 +set_property PACKAGE_PIN J8 [get_ports {vme_sysreset_n_i}] +set_property IOSTANDARD LVCMOS25 [get_ports {vme_sysreset_n_i}] +# PadFunction: IO_L12N_T1_MRCC_32 +set_property PACKAGE_PIN AC16 [get_ports {sfpga_rx_i[0]}] +set_property IOSTANDARD SSTL2 [get_ports {sfpga_rx_i[0]}] +# PadFunction: IO_L18N_T2_32 +set_property PACKAGE_PIN AB20 [get_ports {sfpga_rx_i[1]}] +set_property IOSTANDARD SSTL2 [get_ports {sfpga_rx_i[1]}] +# PadFunction: IO_L12N_T1_MRCC_33 +set_property PACKAGE_PIN AD9 [get_ports {sfpga_rx_i[2]}] +set_property IOSTANDARD SSTL2 [get_ports {sfpga_rx_i[2]}] +# PadFunction: IO_L14N_T2_SRCC_33 +set_property PACKAGE_PIN AB10 [get_ports {sfpga_rx_i[3]}] +set_property IOSTANDARD SSTL2 [get_ports {sfpga_rx_i[3]}] +# PadFunction: IO_L16P_T2_33 +set_property PACKAGE_PIN AA13 [get_ports {sfpga_rx_i[4]}] +set_property IOSTANDARD SSTL2 [get_ports {sfpga_rx_i[4]}] +# PadFunction: IO_L16N_T2_33 +set_property PACKAGE_PIN AA12 [get_ports {sfpga_tx_o[0]}] +set_property IOSTANDARD SSTL2 [get_ports {sfpga_tx_o[0]}] +# PadFunction: IO_L17P_T2_33 +set_property PACKAGE_PIN AC13 [get_ports {sfpga_tx_o[1]}] +set_property IOSTANDARD SSTL2 [get_ports {sfpga_tx_o[1]}] +# PadFunction: IO_L17N_T2_33 +set_property PACKAGE_PIN AD13 [get_ports {sfpga_tx_o[2]}] +set_property IOSTANDARD SSTL2 [get_ports {sfpga_tx_o[2]}] +# PadFunction: IO_L18P_T2_33 +set_property PACKAGE_PIN Y13 [get_ports {sfpga_tx_o[3]}] +set_property IOSTANDARD SSTL2 [get_ports {sfpga_tx_o[3]}] +# PadFunction: IO_L18N_T2_33 +set_property PACKAGE_PIN Y12 [get_ports {sfpga_tx_o[4]}] +set_property IOSTANDARD SSTL2 [get_ports {sfpga_tx_o[4]}] +# PadFunction: IO_L20P_T3_33 +set_property PACKAGE_PIN AD10 [get_ports {sfpga_clk_p_o}] +set_property IOSTANDARD DIFF_SSTL2 [get_ports {sfpga_clk_p_o}] +# PadFunction: IO_L20N_T3_33 +set_property PACKAGE_PIN AE10 [get_ports {sfpga_clk_n_o}] +set_property IOSTANDARD DIFF_SSTL2 [get_ports {sfpga_clk_n_o}] +# PadFunction: IO_L1P_T0_16 +set_property PACKAGE_PIN H9 [get_ports {pll20dac_din_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {pll20dac_din_o}] +# PadFunction: IO_L1N_T0_16 +set_property PACKAGE_PIN H8 [get_ports {pll20dac_sclk_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {pll20dac_sclk_o}] +# PadFunction: IO_L2P_T0_16 +set_property PACKAGE_PIN G10 [get_ports {pll20dac_sync_n_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {pll20dac_sync_n_o}] +# PadFunction: IO_L2N_T0_16 +set_property PACKAGE_PIN G9 [get_ports {pll25dac_din_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {pll25dac_din_o}] +# PadFunction: IO_L3P_T0_DQS_16 +set_property PACKAGE_PIN J13 [get_ports {pll25dac_sclk_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {pll25dac_sclk_o}] +# PadFunction: IO_L3N_T0_DQS_16 +set_property PACKAGE_PIN H13 [get_ports {pll25dac_sync_n_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {pll25dac_sync_n_o}] +# PadFunction: MGTXTXP0_115 +set_property PACKAGE_PIN P2 [get_ports {sfp_txp_o}] +set_property IOSTANDARD LVCMOS33 [get_ports {sfp_txp_o}] +# PadFunction: MGTXTXN0_115 +set_property PACKAGE_PIN P1 [get_ports {sfp_txn_o}] +set_property IOSTANDARD LVCMOS33 [get_ports {sfp_txn_o}] +# PadFunction: MGTXRXP0_115 +set_property PACKAGE_PIN R4 [get_ports {sfp_rxp_i}] +set_property IOSTANDARD LVCMOS33 [get_ports {sfp_rxp_i}] +# PadFunction: MGTXRXN0_115 +set_property PACKAGE_PIN R3 [get_ports {sfp_rxn_i}] +set_property IOSTANDARD LVCMOS33 [get_ports {sfp_rxn_i}] +# PadFunction: MGTXTXP3_116 +set_property PACKAGE_PIN A4 [get_ports {fmc0_dp_txp_o[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {fmc0_dp_txp_o[3]}] +# PadFunction: MGTXTXP2_116 +set_property PACKAGE_PIN B2 [get_ports {fmc0_dp_txp_o[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {fmc0_dp_txp_o[2]}] +# PadFunction: MGTXTXP1_116 +set_property PACKAGE_PIN D2 [get_ports {fmc0_dp_txp_o[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {fmc0_dp_txp_o[1]}] +# PadFunction: MGTXTXP0_116 +set_property PACKAGE_PIN F2 [get_ports {fmc0_dp_txp_o[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {fmc0_dp_txp_o[0]}] +# PadFunction: MGTXRXP3_116 +set_property PACKAGE_PIN B6 [get_ports {fmc0_dp_rxp_i[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {fmc0_dp_rxp_i[3]}] +# PadFunction: MGTXRXP2_116 +set_property PACKAGE_PIN C4 [get_ports {fmc0_dp_rxp_i[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {fmc0_dp_rxp_i[2]}] +# PadFunction: MGTXRXP1_116 +set_property PACKAGE_PIN E4 [get_ports {fmc0_dp_rxp_i[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {fmc0_dp_rxp_i[1]}] +# PadFunction: MGTXRXP0_116 +set_property PACKAGE_PIN G4 [get_ports {fmc0_dp_rxp_i[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {fmc0_dp_rxp_i[0]}] +# PadFunction: MGTREFCLK0P_116 +set_property PACKAGE_PIN D6 [get_ports {fmc0_dp_clk_p_i}] +set_property IOSTANDARD LVCMOS33 [get_ports {fmc0_dp_clk_p_i}] +# PadFunction: MGTXTXP1_115 +set_property PACKAGE_PIN M2 [get_ports {fmc1_dp_txp_o}] +set_property IOSTANDARD LVCMOS33 [get_ports {fmc1_dp_txp_o}] +# PadFunction: MGTXRXP1_115 +set_property PACKAGE_PIN N4 [get_ports {fmc1_dp_rxp_i}] +set_property IOSTANDARD LVCMOS33 [get_ports {fmc1_dp_rxp_i}] +# PadFunction: MGTXTXP2_115 +set_property PACKAGE_PIN K2 [get_ports {dp0_txp_o}] +set_property IOSTANDARD LVCMOS33 [get_ports {dp0_txp_o}] +# PadFunction: MGTXRXP2_115 +set_property PACKAGE_PIN L4 [get_ports {dp0_rxp_i}] +set_property IOSTANDARD LVCMOS33 [get_ports {dp0_rxp_i}] +# PadFunction: MGTXTXP3_115 +set_property PACKAGE_PIN H2 [get_ports {dp1_txp_o}] +set_property IOSTANDARD LVCMOS33 [get_ports {dp1_txp_o}] +# PadFunction: MGTXRXP3_115 +set_property PACKAGE_PIN J4 [get_ports {dp1_rxp_i}] +set_property IOSTANDARD LVCMOS33 [get_ports {dp1_rxp_i}] +# PadFunction: MGTREFCLK0P_115 +set_property PACKAGE_PIN H6 [get_ports {clk_125m_gtx_p_i}] +set_property IOSTANDARD LVCMOS33 [get_ports {clk_125m_gtx_p_i}] +# PadFunction: MGTREFCLK1P_115 +set_property PACKAGE_PIN K6 [get_ports {fmc1_dp_clk_p_i}] +set_property IOSTANDARD LVCMOS33 [get_ports {fmc1_dp_clk_p_i}] +# PadFunction: IO_L1N_T0_D01_DIN_14 +set_property PACKAGE_PIN A25 [get_ports {flash_miso_i}] +set_property IOSTANDARD LVCMOS25 [get_ports {flash_miso_i}] +# PadFunction: IO_L1P_T0_D00_MOSI_14 +set_property PACKAGE_PIN B24 [get_ports {flash_mosi_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {flash_mosi_o}] +# PadFunction: IO_L6P_T0_FCS_B_14 +set_property PACKAGE_PIN C23 [get_ports {flash_cs_n_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {flash_cs_n_o}] +# PadFunction: IO_L4P_T0_16 +set_property PACKAGE_PIN J11 [get_ports {fmc0_tck_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_tck_o}] +# PadFunction: IO_L4N_T0_16 +set_property PACKAGE_PIN J10 [get_ports {fmc0_tms_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_tms_o}] +# PadFunction: IO_L5P_T0_16 +set_property PACKAGE_PIN H14 [get_ports {fmc0_tdi_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_tdi_o}] +# PadFunction: IO_L5N_T0_16 +set_property PACKAGE_PIN G14 [get_ports {fmc0_tdo_i}] +set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_tdo_i}] +# PadFunction: IO_L6P_T0_16 +set_property PACKAGE_PIN H12 [get_ports {fmc1_tck_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_tck_o}] +# PadFunction: IO_L7P_T1_16 +set_property PACKAGE_PIN F9 [get_ports {fmc1_tms_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_tms_o}] +# PadFunction: IO_L7N_T1_16 +set_property PACKAGE_PIN F8 [get_ports {fmc1_tdi_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_tdi_o}] +# PadFunction: IO_L8P_T1_16 +set_property PACKAGE_PIN D9 [get_ports {fmc1_tdo_i}] +set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_tdo_i}] +# PadFunction: IO_L8N_T1_16 +set_property PACKAGE_PIN D8 [get_ports {ioexp_reset_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {ioexp_reset_o}] +# PadFunction: IO_L9P_T1_DQS_16 +set_property PACKAGE_PIN A9 [get_ports {ioexp_sclk_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {ioexp_sclk_o}] +# PadFunction: IO_L9N_T1_DQS_16 +set_property PACKAGE_PIN A8 [get_ports {ioexp_rclk_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {ioexp_rclk_o}] +# PadFunction: IO_L10P_T1_16 +set_property PACKAGE_PIN C9 [get_ports {ioexp_rclk_power_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {ioexp_rclk_power_o}] +# PadFunction: IO_L10N_T1_16 +set_property PACKAGE_PIN B9 [get_ports {ioexp_d_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {ioexp_d_o}] +# PadFunction: IO_L11P_T1_SRCC_16 +set_property PACKAGE_PIN G11 [get_ports {ioexp_d_i}] +set_property IOSTANDARD LVCMOS25 [get_ports {ioexp_d_i}] +# PadFunction: IO_L11N_T1_SRCC_16 +set_property PACKAGE_PIN F10 [get_ports {sfp_mod_def1_b}] +set_property IOSTANDARD LVCMOS25 [get_ports {sfp_mod_def1_b}] +# PadFunction: IO_L14P_T2_SRCC_16 +set_property PACKAGE_PIN E11 [get_ports {sfp_mod_def2_b}] +set_property IOSTANDARD LVCMOS25 [get_ports {sfp_mod_def2_b}] +# PadFunction: IO_L14N_T2_SRCC_16 +set_property PACKAGE_PIN D11 [get_ports {carrier_scl_b}] +set_property IOSTANDARD LVCMOS25 [get_ports {carrier_scl_b}] +# PadFunction: IO_L15P_T2_DQS_16 +set_property PACKAGE_PIN F14 [get_ports {carrier_sda_b}] +set_property IOSTANDARD LVCMOS25 [get_ports {carrier_sda_b}] +# PadFunction: IO_L15N_T2_DQS_16 +set_property PACKAGE_PIN F13 [get_ports {onewire_b}] +set_property IOSTANDARD LVCMOS25 [get_ports {onewire_b}] +# PadFunction: IO_L16P_T2_16 +set_property PACKAGE_PIN G12 [get_ports {uart_rxd_i}] +set_property IOSTANDARD LVCMOS25 [get_ports {uart_rxd_i}] +# PadFunction: IO_L16N_T2_16 +set_property PACKAGE_PIN F12 [get_ports {uart_txd_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {uart_txd_o}] +# PadFunction: IO_L17P_T2_16 +set_property PACKAGE_PIN D14 [get_ports {ddr3_spd_scl_b}] +set_property IOSTANDARD LVCMOS25 [get_ports {ddr3_spd_scl_b}] +# PadFunction: IO_L17N_T2_16 +set_property PACKAGE_PIN D13 [get_ports {ddr3_spd_sda_b}] +set_property IOSTANDARD LVCMOS25 [get_ports {ddr3_spd_sda_b}] +# PadFunction: IO_L18P_T2_16 +set_property PACKAGE_PIN E13 [get_ports {fp_gpio1_b}] +set_property IOSTANDARD LVCMOS25 [get_ports {fp_gpio1_b}] +# PadFunction: IO_L18N_T2_16 +set_property PACKAGE_PIN E12 [get_ports {fp_gpio2_b}] +set_property IOSTANDARD LVCMOS25 [get_ports {fp_gpio2_b}] +# PadFunction: IO_L14P_T2_SRCC_14 +set_property PACKAGE_PIN G24 [get_ports {fp_gpio3_b}] +set_property IOSTANDARD LVCMOS25 [get_ports {fp_gpio3_b}] +# PadFunction: IO_L19P_T3_16 +set_property PACKAGE_PIN C14 [get_ports {fp_gpio4_b}] +set_property IOSTANDARD LVCMOS25 [get_ports {fp_gpio4_b}] +# PadFunction: IO_L20P_T3_16 +set_property PACKAGE_PIN B12 [get_ports {fmc0_scl_b}] +set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_scl_b}] +# PadFunction: IO_L20N_T3_16 +set_property PACKAGE_PIN B11 [get_ports {fmc0_sda_b}] +set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_sda_b}] +# PadFunction: IO_L21P_T3_DQS_16 +set_property PACKAGE_PIN B14 [get_ports {fmc1_scl_b}] +set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_scl_b}] +# PadFunction: IO_L21N_T3_DQS_16 +set_property PACKAGE_PIN A14 [get_ports {fmc1_sda_b}] +set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_sda_b}] +# PadFunction: IO_L22P_T3_16 +set_property PACKAGE_PIN B10 [get_ports {si57x_scl_b}] +set_property IOSTANDARD LVCMOS25 [get_ports {si57x_scl_b}] +# PadFunction: IO_L22N_T3_16 +set_property PACKAGE_PIN A10 [get_ports {si57x_sda_b}] +set_property IOSTANDARD LVCMOS25 [get_ports {si57x_sda_b}] +# PadFunction: IO_L23P_T3_16 +set_property PACKAGE_PIN B15 [get_ports {si57x_tune_o}] +set_property IOSTANDARD LVCMOS25 [get_ports {si57x_tune_o}] diff --git a/hdl/syn/svec7_test/buildinfo_pkg.vhd b/hdl/syn/svec7_test/buildinfo_pkg.vhd new file mode 100644 index 0000000..bbef055 --- /dev/null +++ b/hdl/syn/svec7_test/buildinfo_pkg.vhd @@ -0,0 +1,13 @@ +-- Buildinfo for project svec7_test_top +-- +-- This file was automatically generated; do not edit + +package buildinfo_pkg is + constant buildinfo : string := + "buildinfo:1" & LF + & "module:svec7_test_top" & LF + & "commit:37d6449f7beb462d0bbb4dc73e42d4aa5371a2c0" & LF + & "syntool:vivado" & LF + & "syndate:2019-12-10, 15:24 CET" & LF + & "synauth:Tomasz Wlostowski" & LF; +end buildinfo_pkg; -- 2.18.1