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Simple VME FMC Carrier SVEC
Commits
bc5bb9fa
Commit
bc5bb9fa
authored
Apr 07, 2020
by
Tristan Gingold
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tester_wr: add fpga-dev-id
parent
7033fc15
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6 changed files
with
289 additions
and
45 deletions
+289
-45
Manifest.py
hdl/top/tester_wr/Manifest.py
+1
-1
svec_tester_wr.vhd
hdl/top/tester_wr/svec_tester_wr.vhd
+3
-2
tester_top_regs.cheby
hdl/top/tester_wr/tester_top_regs.cheby
+13
-0
tester_top_regs.vhd
hdl/top/tester_wr/tester_top_regs.vhd
+128
-16
tester_wr_regs.cheby
hdl/top/tester_wr/tester_wr_regs.cheby
+59
-1
tester_wr_regs.h
hdl/top/tester_wr/tester_wr_regs.h
+85
-25
No files found.
hdl/top/tester_wr/Manifest.py
View file @
bc5bb9fa
files
=
[
"svec_tester_wr.vhd"
,
"tester_
wr
_regs.vhd"
]
files
=
[
"svec_tester_wr.vhd"
,
"tester_
top
_regs.vhd"
]
modules
=
{
'local'
:
[
"../../rtl"
]}
hdl/top/tester_wr/svec_tester_wr.vhd
View file @
bc5bb9fa
...
...
@@ -236,13 +236,14 @@ architecture top of svec_tester_wr is
begin
inst_svec_base
:
entity
work
.
svec_base_wr
generic
map
(
g_DECODE_AM
=>
False
,
g_with_vic
=>
True
,
g_with_onewire
=>
False
,
g_with_spi
=>
True
,
g_with_wr
=>
True
,
g_with_ddr4
=>
False
,
g_with_ddr5
=>
False
,
g_app_offset
=>
x"0000_
0
000"
,
g_app_offset
=>
x"0000_
2
000"
,
g_num_user_irq
=>
1
,
g_dpram_initf
=>
g_dpram_initf
,
g_fabric_iface
=>
open
,
...
...
@@ -462,7 +463,7 @@ begin
fp_gpio2_a2b_o
<=
'1'
;
fp_gpio34_a2b_o
<=
'1'
;
inst_regs
:
entity
work
.
tester_
wr
_regs
inst_regs
:
entity
work
.
tester_
top
_regs
port
map
(
rst_n_i
=>
rst_sys_62m5_n
,
clk_i
=>
clk_sys_62m5
,
...
...
hdl/top/tester_wr/tester_top_regs.cheby
0 → 100644
View file @
bc5bb9fa
memory-map:
bus: wb-32-be
name: tester_top_regs
description: Memory map of the SVEC tester board
x-hdl:
busgroup: True
block-prefix: False
children:
- submap:
address: 0x2000
name: tester_wr
filename: tester_wr_regs.cheby
include: True
hdl/top/tester_wr/tester_
wr
_regs.vhd
→
hdl/top/tester_wr/tester_
top
_regs.vhd
View file @
bc5bb9fa
-- Do not edit. Generated on
Mon Apr 06 15:32:18
2020 by tgingold
-- Do not edit. Generated on
Tue Apr 07 14:01:51
2020 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- -i tester_
wr
_regs.cheby --gen-hdl
-- -i tester_
top
_regs.cheby --gen-hdl
library
ieee
;
...
...
@@ -8,7 +8,7 @@ use ieee.std_logic_1164.all;
use
ieee
.
numeric_std
.
all
;
use
work
.
wishbone_pkg
.
all
;
entity
tester_
wr
_regs
is
entity
tester_
top
_regs
is
port
(
rst_n_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
...
...
@@ -18,7 +18,7 @@ entity tester_wr_regs is
-- General status
-- Set when WR has time
status_time_valid_i
:
in
std_logic
;
-- Set when WR has
time
-- Set when WR has
link
status_link_valid_i
:
in
std_logic
;
-- TAI from wr
...
...
@@ -49,9 +49,9 @@ entity tester_wr_regs is
-- number of interrupts successfully ack-ed; cleared at the start
ack_count_i
:
in
std_logic_vector
(
31
downto
0
)
);
end
tester_
wr
_regs
;
end
tester_
top
_regs
;
architecture
syn
of
tester_
wr
_regs
is
architecture
syn
of
tester_
top
_regs
is
signal
adr_int
:
std_logic_vector
(
13
downto
2
);
signal
rd_req_int
:
std_logic
;
signal
wr_req_int
:
std_logic
;
...
...
@@ -133,6 +133,22 @@ begin
end
if
;
end
process
;
-- Register vendor_id
-- Register device_id
-- Register version
-- Register bom
-- Register source_id0
-- Register source_id1
-- Register source_id2
-- Register source_id3
-- Register status
-- Register tm_tai
...
...
@@ -232,15 +248,59 @@ begin
total_count_wreq
<=
'0'
;
ack_int_wreq
<=
'0'
;
case
wr_adr_d0
(
13
downto
3
)
is
when
"10000000000"
=>
case
wr_adr_d0
(
2
downto
2
)
is
when
"0"
=>
-- Reg vendor_id
wr_ack_int
<=
wr_req_d0
;
when
"1"
=>
-- Reg device_id
wr_ack_int
<=
wr_req_d0
;
when
others
=>
wr_ack_int
<=
wr_req_d0
;
end
case
;
when
"10000000001"
=>
case
wr_adr_d0
(
2
downto
2
)
is
when
"0"
=>
-- Reg status
-- Reg version
wr_ack_int
<=
wr_req_d0
;
when
"1"
=>
-- Reg bom
wr_ack_int
<=
wr_req_d0
;
when
others
=>
wr_ack_int
<=
wr_req_d0
;
end
case
;
when
"10000000010"
=>
case
wr_adr_d0
(
2
downto
2
)
is
when
"0"
=>
-- Reg source_id0
wr_ack_int
<=
wr_req_d0
;
when
"1"
=>
-- Reg source_id1
wr_ack_int
<=
wr_req_d0
;
when
others
=>
wr_ack_int
<=
wr_req_d0
;
end
case
;
when
"10000000011"
=>
case
wr_adr_d0
(
2
downto
2
)
is
when
"0"
=>
-- Reg source_id2
wr_ack_int
<=
wr_req_d0
;
when
"1"
=>
-- Reg source_id3
wr_ack_int
<=
wr_req_d0
;
when
others
=>
wr_ack_int
<=
wr_req_d0
;
end
case
;
when
"10000000100"
=>
case
wr_adr_d0
(
2
downto
2
)
is
when
"0"
=>
-- Reg status
wr_ack_int
<=
wr_req_d0
;
when
others
=>
wr_ack_int
<=
wr_req_d0
;
end
case
;
when
"10000000101"
=>
case
wr_adr_d0
(
2
downto
2
)
is
when
"0"
=>
-- Reg tm_tai
...
...
@@ -251,7 +311,7 @@ begin
when
others
=>
wr_ack_int
<=
wr_req_d0
;
end
case
;
when
"10000000
011
"
=>
when
"10000000
110
"
=>
case
wr_adr_d0
(
2
downto
2
)
is
when
"0"
=>
-- Reg tm_cycles
...
...
@@ -263,7 +323,7 @@ begin
when
others
=>
wr_ack_int
<=
wr_req_d0
;
end
case
;
when
"100000001
00
"
=>
when
"100000001
11
"
=>
case
wr_adr_d0
(
2
downto
2
)
is
when
"0"
=>
-- Reg start_cycles
...
...
@@ -276,7 +336,7 @@ begin
when
others
=>
wr_ack_int
<=
wr_req_d0
;
end
case
;
when
"1000000
0101
"
=>
when
"1000000
1000
"
=>
case
wr_adr_d0
(
2
downto
2
)
is
when
"0"
=>
-- Reg total_count
...
...
@@ -288,7 +348,7 @@ begin
when
others
=>
wr_ack_int
<=
wr_req_d0
;
end
case
;
when
"1000000
0110
"
=>
when
"1000000
1001
"
=>
case
wr_adr_d0
(
2
downto
2
)
is
when
"0"
=>
-- Reg ack_int
...
...
@@ -310,7 +370,59 @@ begin
-- By default ack read requests
rd_dat_d0
<=
(
others
=>
'X'
);
case
adr_int
(
13
downto
3
)
is
when
"10000000000"
=>
case
adr_int
(
2
downto
2
)
is
when
"0"
=>
-- Reg vendor_id
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
<=
"00000000000000000001000011011100"
;
when
"1"
=>
-- Reg device_id
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
<=
"01010100010100110101010000000001"
;
when
others
=>
rd_ack_d0
<=
rd_req_int
;
end
case
;
when
"10000000001"
=>
case
adr_int
(
2
downto
2
)
is
when
"0"
=>
-- Reg version
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
<=
"00000000000000000000000000000001"
;
when
"1"
=>
-- Reg bom
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
<=
"11111111111111100000000000000000"
;
when
others
=>
rd_ack_d0
<=
rd_req_int
;
end
case
;
when
"10000000010"
=>
case
adr_int
(
2
downto
2
)
is
when
"0"
=>
-- Reg source_id0
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
<=
"00000000000000000000000000000000"
;
when
"1"
=>
-- Reg source_id1
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
<=
"00000000000000000000000000000000"
;
when
others
=>
rd_ack_d0
<=
rd_req_int
;
end
case
;
when
"10000000011"
=>
case
adr_int
(
2
downto
2
)
is
when
"0"
=>
-- Reg source_id2
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
<=
"00000000000000000000000000000000"
;
when
"1"
=>
-- Reg source_id3
rd_ack_d0
<=
rd_req_int
;
rd_dat_d0
<=
"00000000000000000000000000000000"
;
when
others
=>
rd_ack_d0
<=
rd_req_int
;
end
case
;
when
"10000000100"
=>
case
adr_int
(
2
downto
2
)
is
when
"0"
=>
-- Reg status
...
...
@@ -321,7 +433,7 @@ begin
when
others
=>
rd_ack_d0
<=
rd_req_int
;
end
case
;
when
"10000000
010
"
=>
when
"10000000
101
"
=>
case
adr_int
(
2
downto
2
)
is
when
"0"
=>
-- Reg tm_tai
...
...
@@ -334,7 +446,7 @@ begin
when
others
=>
rd_ack_d0
<=
rd_req_int
;
end
case
;
when
"10000000
011
"
=>
when
"10000000
110
"
=>
case
adr_int
(
2
downto
2
)
is
when
"0"
=>
-- Reg tm_cycles
...
...
@@ -347,7 +459,7 @@ begin
when
others
=>
rd_ack_d0
<=
rd_req_int
;
end
case
;
when
"100000001
00
"
=>
when
"100000001
11
"
=>
case
adr_int
(
2
downto
2
)
is
when
"0"
=>
-- Reg start_cycles
...
...
@@ -360,7 +472,7 @@ begin
when
others
=>
rd_ack_d0
<=
rd_req_int
;
end
case
;
when
"1000000
0101
"
=>
when
"1000000
1000
"
=>
case
adr_int
(
2
downto
2
)
is
when
"0"
=>
-- Reg total_count
...
...
@@ -373,7 +485,7 @@ begin
when
others
=>
rd_ack_d0
<=
rd_req_int
;
end
case
;
when
"1000000
0110
"
=>
when
"1000000
1001
"
=>
case
adr_int
(
2
downto
2
)
is
when
"0"
=>
-- Reg ack_int
...
...
hdl/top/tester_wr/tester_wr_regs.cheby
View file @
bc5bb9fa
...
...
@@ -5,10 +5,68 @@ memory-map:
x-hdl:
busgroup: True
children:
- block:
name: dev_id
children:
- reg:
name: vendor_id
access: ro
width: 32
preset: 0x10dc
x-hdl:
type: const
- reg:
name: device_id
access: ro
width: 32
preset: 0x54535401
x-hdl:
type: const
- reg:
name: version
access: ro
width: 32
preset: 0x00000001
x-hdl:
type: const
- reg:
name: bom
access: ro
width: 32
preset: 0xfffe0000
x-hdl:
type: const
- reg:
name: source_id0
access: ro
width: 32
preset: 0
x-hdl:
type: const
- reg:
name: source_id1
access: ro
width: 32
preset: 0
x-hdl:
type: const
- reg:
name: source_id2
access: ro
width: 32
preset: 0
x-hdl:
type: const
- reg:
name: source_id3
access: ro
width: 32
preset: 0
x-hdl:
type: const
- reg:
name: status
description: General status
address: 0x2008
width: 32
access: ro
children:
...
...
hdl/top/tester_wr/tester_wr_regs.h
View file @
bc5bb9fa
#ifndef __CHEBY__TESTER_WR_REGS__H__
#define __CHEBY__TESTER_WR_REGS__H__
#define TESTER_WR_REGS_SIZE 8248
#define TESTER_WR_REGS_SIZE 80
/* None */
#define TESTER_WR_REGS_DEV_ID 0x0UL
#define TESTER_WR_REGS_DEV_ID_SIZE 32
/* None */
#define TESTER_WR_REGS_DEV_ID_VENDOR_ID 0x0UL
#define TESTER_WR_REGS_DEV_ID_VENDOR_ID_PRESET 0x10dcUL
/* None */
#define TESTER_WR_REGS_DEV_ID_DEVICE_ID 0x4UL
#define TESTER_WR_REGS_DEV_ID_DEVICE_ID_PRESET 0x54535401UL
/* None */
#define TESTER_WR_REGS_DEV_ID_VERSION 0x8UL
#define TESTER_WR_REGS_DEV_ID_VERSION_PRESET 0x1UL
/* None */
#define TESTER_WR_REGS_DEV_ID_BOM 0xcUL
#define TESTER_WR_REGS_DEV_ID_BOM_PRESET 0xfffe0000UL
/* None */
#define TESTER_WR_REGS_DEV_ID_SOURCE_ID0 0x10UL
#define TESTER_WR_REGS_DEV_ID_SOURCE_ID0_PRESET 0x0UL
/* None */
#define TESTER_WR_REGS_DEV_ID_SOURCE_ID1 0x14UL
#define TESTER_WR_REGS_DEV_ID_SOURCE_ID1_PRESET 0x0UL
/* None */
#define TESTER_WR_REGS_DEV_ID_SOURCE_ID2 0x18UL
#define TESTER_WR_REGS_DEV_ID_SOURCE_ID2_PRESET 0x0UL
/* None */
#define TESTER_WR_REGS_DEV_ID_SOURCE_ID3 0x1cUL
#define TESTER_WR_REGS_DEV_ID_SOURCE_ID3_PRESET 0x0UL
/* General status */
#define TESTER_WR_REGS_STATUS 0x20
08
UL
#define TESTER_WR_REGS_STATUS 0x20UL
#define TESTER_WR_REGS_STATUS_TIME_VALID 0x1UL
#define TESTER_WR_REGS_STATUS_LINK_VALID 0x2UL
/* TAI from wr */
#define TESTER_WR_REGS_TM_TAI 0x2
010
UL
#define TESTER_WR_REGS_TM_TAI 0x2
8
UL
/* number of cycles (16Mhz) within the second */
#define TESTER_WR_REGS_TM_CYCLES 0x
2018
UL
#define TESTER_WR_REGS_TM_CYCLES 0x
30
UL
/* absolute TAI (LSB) for interrupts */
#define TESTER_WR_REGS_START_TAI 0x
201c
UL
#define TESTER_WR_REGS_START_TAI 0x
34
UL
/* absolute cycles for interrupts */
#define TESTER_WR_REGS_START_CYCLES 0x
2020
UL
#define TESTER_WR_REGS_START_CYCLES 0x
38
UL
/* number of cycles between interrupts */
#define TESTER_WR_REGS_PERIOD_CYCLES 0x
2024
UL
#define TESTER_WR_REGS_PERIOD_CYCLES 0x
3c
UL
/* number of interrupts to deliver */
#define TESTER_WR_REGS_TOTAL_COUNT 0x
2028
UL
#define TESTER_WR_REGS_TOTAL_COUNT 0x
40
UL
/* number of interrupts delivered. */
#define TESTER_WR_REGS_CURRENT_COUNT 0x
202c
UL
#define TESTER_WR_REGS_CURRENT_COUNT 0x
44
UL
/* the current number of interrupts must be written to ack the interrupt. */
#define TESTER_WR_REGS_ACK_INT 0x
2030
UL
#define TESTER_WR_REGS_ACK_INT 0x
48
UL
/* number of interrupts successfully ack-ed; cleared at the start */
#define TESTER_WR_REGS_ACK_COUNT 0x
2034
UL
#define TESTER_WR_REGS_ACK_COUNT 0x
4c
UL
struct
tester_wr_regs
{
/* [0x0]: BLOCK (no description) */
struct
dev_id
{
/* [0x0]: REG (ro) (no description) */
uint32_t
vendor_id
;
/* [0x4]: REG (ro) (no description) */
uint32_t
device_id
;
/* [0x8]: REG (ro) (no description) */
uint32_t
version
;
/* [0xc]: REG (ro) (no description) */
uint32_t
bom
;
/* [0x10]: REG (ro) (no description) */
uint32_t
source_id0
;
/* [0x14]: REG (ro) (no description) */
uint32_t
source_id1
;
/* [0x18]: REG (ro) (no description) */
uint32_t
source_id2
;
/* [0x1c]: REG (ro) (no description) */
uint32_t
source_id3
;
}
dev_id
;
/* padding to: 2050 words */
uint32_t
__padding_0
[
2050
];
/* [0x2008]: REG (ro) General status */
/* [0x20]: REG (ro) General status */
uint32_t
status
;
/* padding to:
2052
words */
uint32_t
__padding_
1
[
1
];
/* padding to:
10
words */
uint32_t
__padding_
0
[
1
];
/* [0x2
010
]: REG (ro) TAI from wr */
/* [0x2
8
]: REG (ro) TAI from wr */
uint64_t
tm_tai
;
/* [0x
2018
]: REG (ro) number of cycles (16Mhz) within the second */
/* [0x
30
]: REG (ro) number of cycles (16Mhz) within the second */
uint32_t
tm_cycles
;
/* [0x
201c
]: REG (rw) absolute TAI (LSB) for interrupts */
/* [0x
34
]: REG (rw) absolute TAI (LSB) for interrupts */
uint32_t
start_tai
;
/* [0x
2020
]: REG (rw) absolute cycles for interrupts */
/* [0x
38
]: REG (rw) absolute cycles for interrupts */
uint32_t
start_cycles
;
/* [0x
2024
]: REG (rw) number of cycles between interrupts */
/* [0x
3c
]: REG (rw) number of cycles between interrupts */
uint32_t
period_cycles
;
/* [0x
2028
]: REG (rw) number of interrupts to deliver */
/* [0x
40
]: REG (rw) number of interrupts to deliver */
uint32_t
total_count
;
/* [0x
202c
]: REG (ro) number of interrupts delivered. */
/* [0x
44
]: REG (ro) number of interrupts delivered. */
uint32_t
current_count
;
/* [0x
2030
]: REG (wo) the current number of interrupts must be written to ack the interrupt. */
/* [0x
48
]: REG (wo) the current number of interrupts must be written to ack the interrupt. */
uint32_t
ack_int
;
/* [0x
2034
]: REG (ro) number of interrupts successfully ack-ed; cleared at the start */
/* [0x
4c
]: REG (ro) number of interrupts successfully ack-ed; cleared at the start */
uint32_t
ack_count
;
};
...
...
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