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Simple VME FMC Carrier SVEC
Commit bbe9114e authored by Tristan Gingold's avatar Tristan Gingold
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svec template: add ddr registers.

parent a8d09a80
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Showing with 155 additions and 6 deletions
hdl/rtl/svec_template_regs.cheby
View file @ bbe9114e
......@@ -66,6 +66,25 @@ memory-map:
- field:
name: rev
range: 4-0
- reg:
name: ddr4_addr
description: address of data to read or to write
access: rw
width: 32
x-hdl:
type: wire
write-strobe: True
- reg:
name: ddr4_data
description: data to read or to write in ddr4
access: rw
width: 32
x-hdl:
type: wire
read-strobe: True
write-strobe: True
read-ack: True
write-ack: True
- submap:
name: therm_id
description: Thermometer and unique id
......
hdl/rtl/svec_template_regs.vhd
View file @ bbe9114e
-- Do not edit; this file was generated by Cheby using these options:
-- --gen-hdl -i svec_template_regs.cheby
-- --gen-hdl=svec_template_regs.vhd -i svec_template_regs.cheby
library ieee;
use ieee.std_logic_1164.all;
......@@ -26,6 +26,7 @@ entity svec_template_regs is
metadata_addr_o : out std_logic_vector(5 downto 2);
metadata_data_i : in std_logic_vector(31 downto 0);
metadata_data_o : out std_logic_vector(31 downto 0);
metadata_wr_o : out std_logic;
-- offset to the application metadata
csr_app_offset_i : in std_logic_vector(31 downto 0);
......@@ -35,13 +36,26 @@ entity svec_template_regs is
-- presence lines for the fmcs
csr_fmc_presence_i : in std_logic_vector(31 downto 0);
-- Set when ddr5 calibration is done.
-- Set when ddr4 calibration is done.
csr_ddr_status_ddr4_calib_done_i : in std_logic;
-- Set when ddr4 calibration is done.
-- Set when ddr5 calibration is done.
csr_ddr_status_ddr5_calib_done_i : in std_logic;
csr_pcb_rev_rev_i : in std_logic_vector(4 downto 0);
-- address of data to read or to write
csr_ddr4_addr_i : in std_logic_vector(31 downto 0);
csr_ddr4_addr_o : out std_logic_vector(31 downto 0);
csr_ddr4_addr_wr_o : out std_logic;
-- data to read or to write in ddr4
csr_ddr4_data_i : in std_logic_vector(31 downto 0);
csr_ddr4_data_o : out std_logic_vector(31 downto 0);
csr_ddr4_data_wr_o : out std_logic;
csr_ddr4_data_rd_o : out std_logic;
csr_ddr4_data_wack_i : in std_logic;
csr_ddr4_data_rack_i : in std_logic;
-- Thermometer and unique id
therm_id_i : in t_wishbone_master_in;
therm_id_o : out t_wishbone_master_out;
......@@ -62,6 +76,7 @@ entity svec_template_regs is
buildinfo_addr_o : out std_logic_vector(7 downto 2);
buildinfo_data_i : in std_logic_vector(31 downto 0);
buildinfo_data_o : out std_logic_vector(31 downto 0);
buildinfo_wr_o : out std_logic;
-- white-rabbit core registers
wrc_regs_i : in t_wishbone_master_in;
......@@ -261,19 +276,27 @@ begin
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wr_ack_int <= '0';
metadata_wr_o <= '0';
csr_resets_global_reg <= '0';
csr_resets_appl_reg <= '0';
csr_ddr4_addr_wr_o <= '0';
csr_ddr4_data_wr_o <= '0';
therm_id_wt <= '0';
fmc_i2c_wt <= '0';
flash_spi_wt <= '0';
vic_wt <= '0';
buildinfo_wr_o <= '0';
wrc_regs_wt <= '0';
elsif rising_edge(clk_i) then
wr_ack_int <= '0';
metadata_wr_o <= '0';
csr_ddr4_addr_wr_o <= '0';
csr_ddr4_data_wr_o <= '0';
therm_id_wt <= '0';
fmc_i2c_wt <= '0';
flash_spi_wt <= '0';
vic_wt <= '0';
buildinfo_wr_o <= '0';
wrc_regs_wt <= '0';
case wb_adr_i(12 downto 12) is
when "0" =>
......@@ -282,6 +305,8 @@ begin
case wb_adr_i(7 downto 6) is
when "00" =>
-- Submap metadata
metadata_wr_o <= wr_int;
wr_ack_int <= wr_int;
when "01" =>
case wb_adr_i(5 downto 4) is
when "00" =>
......@@ -308,6 +333,20 @@ begin
-- Register csr_ddr_status
when "01" =>
-- Register csr_pcb_rev
when "10" =>
-- Register csr_ddr4_addr
csr_ddr4_addr_wr_o <= wr_int;
if wr_int = '1' then
csr_ddr4_addr_o <= wb_dat_i;
end if;
wr_ack_int <= wr_int;
when "11" =>
-- Register csr_ddr4_data
csr_ddr4_data_wr_o <= wr_int;
if wr_int = '1' then
csr_ddr4_data_o <= wb_dat_i;
end if;
wr_ack_int <= csr_ddr4_data_wack_i;
when others =>
wr_ack_int <= wr_int;
end case;
......@@ -340,6 +379,8 @@ begin
wr_ack_int <= vic_wack;
when "0010" =>
-- Submap buildinfo
buildinfo_wr_o <= wr_int;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= wr_int;
end case;
......@@ -358,7 +399,9 @@ begin
if rst_n_i = '0' then
rd_ack1_int <= '0';
reg_rdat_int <= (others => 'X');
csr_ddr4_data_rd_o <= '0';
elsif rising_edge(clk_i) then
csr_ddr4_data_rd_o <= '0';
reg_rdat_int <= (others => '0');
case wb_adr_i(12 downto 12) is
when "0" =>
......@@ -401,6 +444,15 @@ begin
-- csr_pcb_rev
reg_rdat_int(4 downto 0) <= csr_pcb_rev_rev_i;
rd_ack1_int <= rd_int;
when "10" =>
-- csr_ddr4_addr
reg_rdat_int <= csr_ddr4_addr_i;
rd_ack1_int <= rd_int;
when "11" =>
-- csr_ddr4_data
reg_rdat_int <= csr_ddr4_data_i;
csr_ddr4_data_rd_o <= '1';
rd_ack1_int <= csr_ddr4_data_rack_i;
when others =>
rd_ack1_int <= rd_int;
end case;
......@@ -484,6 +536,14 @@ begin
-- csr_pcb_rev
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "10" =>
-- csr_ddr4_addr
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "11" =>
-- csr_ddr4_data
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
......
hdl/rtl/svec_template_wr.vhd
View file @ bbe9114e
......@@ -331,6 +331,23 @@ architecture top of svec_template_wr is
signal ddr4_calib_done : std_logic;
signal ddr5_calib_done : std_logic;
-- Address for ddr4.
signal csr_ddr4_addr_out : std_logic_vector(31 downto 0);
signal csr_ddr4_addr_wr : std_logic;
signal csr_ddr4_addr : std_logic_vector(31 downto 0);
-- data to read or to write in ddr4
signal csr_ddr4_data_in : std_logic_vector(31 downto 0);
signal csr_ddr4_data_out : std_logic_vector(31 downto 0);
signal csr_ddr4_data_wr : std_logic;
signal csr_ddr4_data_rd : std_logic;
signal csr_ddr4_data_wack : std_logic;
signal csr_ddr4_data_rack : std_logic;
--
signal ddr4_read_ip : std_logic;
signal ddr4_write_ip : std_logic;
signal ddr4_wb_out : t_wishbone_master_out;
signal ddr4_wb_in : t_wishbone_master_in;
......@@ -534,6 +551,18 @@ begin -- architecture top
csr_ddr_status_ddr5_calib_done_i => ddr5_calib_done,
csr_pcb_rev_rev_i => pcbrev_i,
csr_ddr4_addr_i => csr_ddr4_addr,
csr_ddr4_addr_o => csr_ddr4_addr_out,
csr_ddr4_addr_wr_o => csr_ddr4_addr_wr,
-- data to read or to write in ddr4
csr_ddr4_data_i => csr_ddr4_data_in,
csr_ddr4_data_o => csr_ddr4_data_out,
csr_ddr4_data_wr_o => csr_ddr4_data_wr,
csr_ddr4_data_rd_o => csr_ddr4_data_rd,
csr_ddr4_data_wack_i => csr_ddr4_data_wack,
csr_ddr4_data_rack_i => csr_ddr4_data_rack,
-- Thermometer and unique id
therm_id_i => therm_id_in,
therm_id_o => therm_id_out,
......@@ -1089,7 +1118,43 @@ begin -- architecture top
-- unused Wishbone signals
ddr4_wb_in.err <= '0';
ddr4_wb_in.rty <= '0';
end generate gen_with_ddr4;
p_ddr4_addr: process (clk_sys_62m5)
begin
if rising_edge(clk_sys_62m5) then
if rst_sys_62m5_n = '0' then
csr_ddr4_addr <= x"0000_0000";
elsif csr_ddr4_addr_wr = '1' then
csr_ddr4_addr <= csr_ddr4_addr_out;
elsif ddr4_wb_in.ack = '1' then
csr_ddr4_addr <= std_logic_vector(unsigned(csr_ddr4_addr) + 4);
end if;
end if;
end process;
p_ddr4_ack: process (clk_sys_62m5)
begin
if rising_edge(clk_sys_62m5) then
if rst_sys_62m5_n = '0' then
ddr4_read_ip <= '0';
ddr4_write_ip <= '0';
else
ddr4_read_ip <= csr_ddr4_data_rd or (ddr4_read_ip and not ddr4_wb_in.ack);
ddr4_write_ip <= csr_ddr4_data_wr or (ddr4_write_ip and not ddr4_wb_in.ack);
end if;
end if;
end process;
ddr4_wb_out <= (adr => csr_ddr4_addr,
cyc => csr_ddr4_data_rd or csr_ddr4_data_wr or ddr4_read_ip or ddr4_write_ip,
stb => csr_ddr4_data_rd or csr_ddr4_data_wr,
sel => x"f",
we => csr_ddr4_data_wr,
dat => csr_ddr4_data_out);
csr_ddr4_data_in <= ddr4_wb_in.dat;
csr_ddr4_data_rack <= ddr4_read_ip and ddr4_wb_in.ack;
csr_ddr4_data_wack <= ddr4_write_ip and ddr4_wb_in.ack;
end generate gen_with_ddr4;
gen_without_ddr4 : if not g_WITH_DDR4 generate
ddr4_calib_done <= '0';
......@@ -1116,14 +1181,19 @@ begin -- architecture top
ddr4_wb_o.ack <= '1';
ddr4_wb_o.stall <= '0';
ddr4_wr_fifo_empty_o <= '0';
csr_ddr4_addr <= x"0000_0000";
ddr4_wb_out <= (adr => (others => 'X'), cyc => '0', stb => '0', sel => x"0", we => '0',
dat => (others => 'X'));
csr_ddr4_data_in <= x"0000_0000";
csr_ddr4_data_rack <= csr_ddr4_data_wr;
csr_ddr4_data_wack <= csr_ddr4_data_wr;
end generate gen_without_ddr4;
ddr4_wb_o.err <= '0';
ddr4_wb_o.rty <= '0';
-- TODO
ddr4_wb_out <= (adr => (others => 'X'), cyc => '0', stb => '0', sel => x"0", we => '0',
dat => (others => 'X'));
ddr5_wb_out <= (adr => (others => 'X'), cyc => '0', stb => '0', sel => x"0", we => '0',
dat => (others => 'X'));
end architecture top;
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