svec7: SFPGA top level test with final FPGA Pinout

add3785a · Tomasz Wlostowski · d02d1f4a · add3785a · add3785a
Commit add3785a authored Oct 02, 2020 by Tomasz Wlostowski
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Showing with 193 additions and 138 deletions

svec7_sfpga_top.ucf hdl/top/svec7_sfpga/svec7_sfpga_top.ucf +170 -124

svec7_sfpga_top.vhd hdl/top/svec7_sfpga/svec7_sfpga_top.vhd +23 -14

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--- a/hdl/top/svec7_sfpga/svec7_sfpga_top.ucf
+++ b/hdl/top/svec7_sfpga/svec7_sfpga_top.ucf
--- a/hdl/top/svec7_sfpga/svec7_sfpga_top.vhd
+++ b/hdl/top/svec7_sfpga/svec7_sfpga_top.vhd
@@ -64,6 +64,7 @@ entity svec7_sfpga_top is
      -------------------------------------------------------------------------

      vme_write_n_i    : in    std_logic;
+      vme_sysclk_i : in std_logic;
      vme_sysreset_n_i : in    std_logic;
      vme_retry_oe_o   : out   std_logic;
      vme_retry_n_o    : out   std_logic;
@@ -87,9 +88,17 @@ entity svec7_sfpga_top is
      vme_am_i         : in    std_logic_vector(5 downto 0);
      vme_addr_b       : inout std_logic_vector(31 downto 1);

+      vme_berr_r_i : in std_logic;
+      vme_dtack_r_i : in std_logic;
+      vme_retry_r_i : in std_logic;
      
-      vme_noga_i   : in std_logic_vector(4 downto 0);
-      vme_use_ga_i : in std_logic;
+      
+      vme_trst_i : in std_logic;
+      vme_tck_i : in std_logic;
+      vme_tdi_i : in std_logic;
+      vme_tms_i : in std_logic;
+      vme_tdo_o : out std_logic;
+      vme_tdo_oe_o : out std_logic;
      
      afpga_clk_p_i : in std_logic;
      afpga_clk_n_i : in std_logic;
@@ -97,6 +106,13 @@ entity svec7_sfpga_top is
      afpga_rx_i : in std_logic_vector(4 downto 0);
      afpga_tx_o : out std_logic_vector(4 downto 0);

+      afpga_cso_b_o : out std_logic;
+      afpga_mosi_o : out std_logic;
+      afpga_miso_i : in std_logic;
+      afpga_cclk_o : out std_logic;
+
+
+      pushbutton_i :in std_logic;
      -------------------------------------------------------------------------
      -- AFPGA boot signals
      -------------------------------------------------------------------------
@@ -118,14 +134,7 @@ entity svec7_sfpga_top is

      debugled_n_o : out std_logic_vector(2 downto 1);

-      -------------------------------------------------------------------------
-      -- Slave SPI interface allowing the Application FPGA to access the SPI flash
-      -------------------------------------------------------------------------
-
-      -- afpga_flash_sck_i  : in  std_logic;
-      -- afpga_flash_mosi_i : in  std_logic;
-      -- afpga_flash_cs_n_i : in  std_logic;
-      -- afpga_flash_miso_o : out std_logic;
+      afpga_mode_ctrl_o : out std_logic_vector(2 downto 0);
      
      -- Onboard PLL enable signal. Must be one for the clock system to work.
      pll_ce_o : out std_logic