Commit ab8dbfc6 authored by Federico Vaga's avatar Federico Vaga

fix licenses and make reuse happy

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent c28c2768
Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/
Upstream-Name: svec
Upstream-Contact: Federico Vaga <federico.vaga@cern.ch>
Source: https://ohwr.org/project/svec
Files: doc/*.svg
Copyright: 2020 CERN (home.cern)
License: CC-BY-SA-4.0+
This diff is collapsed.
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
modules = { "local" : [ "hdl/rtl" ] }
if action == "synthesis":
......
# SPDX-License-Identifier: CC0-1.0
# SPDX-License-Identifier: LGPL-2.1-or-later
# SPDX-FileCopyrightText: 2019 CERN
_build
......
.. SPDX-FileCopyrightText: 2022 CERN (home.cern)
..
.. SPDX-License-Identifier: CC-BY-SA-4.0+
================================
Welcome to SVEC's documentation!
================================
......
-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
-- -*- Mode: LUA; tab-width: 2 -*-
-------------------------------------------------------------------------------
......@@ -14,26 +18,6 @@
-------------------------------------------------------------------------------
-- Description: Wishbone register block definition for Xilinx FPGA loader core.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2013 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
peripheral {
name = "SVEC FPGA loader";
......
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
#===============================================================================
# IO Constraints
#===============================================================================
......
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
# DDR0 (bank 4)
NET "ddr4_rzq_b" LOC = L7;
NET "ddr4_we_n_o" LOC = F4;
......
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
# DDR1 (bank 5)
NET "ddr5_rzq_b" LOC = G25;
NET "ddr5_we_n_o" LOC = E26;
......
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
#----------------------------------------
# Xilinx MCB tweaks
#----------------------------------------
......
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
#----------------------------------------
# Front panel IOs
#----------------------------------------
......
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
#----------------------------------------
# Front panel LEDs
#----------------------------------------
......
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
#===============================================================================
# IO Constraints
#===============================================================================
......
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
......
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
#===============================================================================
# IO Location Constraints
#===============================================================================
......
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
......
// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
`include "svec_base_regs.svh"
......
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
vsim -quiet -t 10fs -L unisim work.main
set StdArithNoWarnings 1
......
// SPDX-FileCopyrightText: 2022 CERN (home.cern)
//
// SPDX-License-Identifier: CERN-OHL-W-2.0+
package svec_base_regs_Consts;
localparam SVEC_BASE_REGS_SIZE = 16384;
localparam ADDR_SVEC_BASE_REGS_METADATA = 'h0;
......
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: GPL-2.0-or-later
Makefile.specific
svec-core-fpga.h
\ No newline at end of file
# SPDX-FileCopyrightText: 2021 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# SPDX-License-Identifier: LGPL-2.1-or-later
svec-firmware-version
\ No newline at end of file
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