fix licenses and make reuse happy

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

fix licenses and make reuse happy
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
ab8dbfc6 · Federico Vaga · c28c2768 · ab8dbfc6 · c28c2768 · ab8dbfc6
Commit ab8dbfc6 authored Dec 02, 2022 by Federico Vaga
21 changed files
--- a/.reuse/dep5
+++ b/.reuse/dep5
+Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/
+Upstream-Name: svec
+Upstream-Contact: Federico Vaga <federico.vaga@cern.ch>
+Source: https://ohwr.org/project/svec
+
+Files: doc/*.svg
+Copyright: 2020 CERN (home.cern)
+License: CC-BY-SA-4.0+
--- a/LICENSES/GPL-2.0.txt
+++ b/LICENSES/GPL-2.0.txt
--- a/Manifest.py
+++ b/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 modules = { "local" : [ "hdl/rtl" ] }

 if action == "synthesis":

--- a/doc/.gitignore
+++ b/doc/.gitignore
-# SPDX-License-Identifier: CC0-1.0
+# SPDX-License-Identifier: LGPL-2.1-or-later
 # SPDX-FileCopyrightText: 2019 CERN

 _build

--- a/doc/index.rst
+++ b/doc/index.rst
+.. SPDX-FileCopyrightText: 2022 CERN (home.cern)
+..
+.. SPDX-License-Identifier: CC-BY-SA-4.0+
+
 ================================
 Welcome to SVEC's documentation!
 ================================

--- a/hdl/rtl/bootloader/svec_xloader_wb.wb
+++ b/hdl/rtl/bootloader/svec_xloader_wb.wb
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 -- -*- Mode: LUA; tab-width: 2 -*-

 -------------------------------------------------------------------------------
@@ -14,26 +18,6 @@
 -------------------------------------------------------------------------------
 -- Description: Wishbone register block definition for Xilinx FPGA loader core.
 -------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2013 CERN
--
-- This source file is free software; you can redistribute it   
-- and/or modify it under the terms of the GNU Lesser General   
-- Public License as published by the Free Software Foundation; 
-- either version 2.1 of the License, or (at your option) any   
-- later version.                                               
--
-- This source is distributed in the hope that it will be       
-- useful, but WITHOUT ANY WARRANTY; without even the implied   
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-- PURPOSE.  See the GNU Lesser General Public License for more 
-- details.                                                     
--
-- You should have received a copy of the GNU Lesser General    
-- Public License along with this source; if not, download it   
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------

 peripheral {
   name = "SVEC FPGA loader";

--- a/hdl/syn/common/svec_base_common.ucf
+++ b/hdl/syn/common/svec_base_common.ucf
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 #===============================================================================
 # IO Constraints
 #===============================================================================

--- a/hdl/syn/common/svec_base_ddr4.ucf
+++ b/hdl/syn/common/svec_base_ddr4.ucf
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 # DDR0 (bank 4)
 NET "ddr4_rzq_b"     LOC = L7;
 NET "ddr4_we_n_o"    LOC = F4;

--- a/hdl/syn/common/svec_base_ddr5.ucf
+++ b/hdl/syn/common/svec_base_ddr5.ucf
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 # DDR1 (bank 5)
 NET "ddr5_rzq_b"     LOC = G25;
 NET "ddr5_we_n_o"    LOC = E26;

--- a/hdl/syn/common/svec_base_ddr_common.ucf
+++ b/hdl/syn/common/svec_base_ddr_common.ucf
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 #----------------------------------------
 # Xilinx MCB tweaks
 #----------------------------------------

--- a/hdl/syn/common/svec_base_gpio.ucf
+++ b/hdl/syn/common/svec_base_gpio.ucf
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 #----------------------------------------
 # Front panel IOs
 #----------------------------------------

--- a/hdl/syn/common/svec_base_led.ucf
+++ b/hdl/syn/common/svec_base_led.ucf
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 #----------------------------------------
 # Front panel LEDs
 #----------------------------------------

--- a/hdl/syn/common/svec_base_wr.ucf
+++ b/hdl/syn/common/svec_base_wr.ucf
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 #===============================================================================
 # IO Constraints
 #===============================================================================

--- a/hdl/syn/golden/syn_extra_steps.tcl
+++ b/hdl/syn/golden/syn_extra_steps.tcl
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 # get project file from 1st command-line argument
 set project_file [lindex $argv 0]


--- a/hdl/syn/sfpga_bootloader/svec_sfpga_top.ucf
+++ b/hdl/syn/sfpga_bootloader/svec_sfpga_top.ucf
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 #===============================================================================
 # IO Location Constraints
 #===============================================================================

--- a/hdl/syn/wr_example/syn_extra_steps.tcl
+++ b/hdl/syn/wr_example/syn_extra_steps.tcl
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 # get project file from 1st command-line argument
 set project_file [lindex $argv 0]


--- a/hdl/testbench/golden/main.sv
+++ b/hdl/testbench/golden/main.sv
+// SPDX-FileCopyrightText: 2022 CERN (home.cern)
+//
+// SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 `include "vme64x_bfm.svh"
 `include "svec_vme_buffers.svh"
 `include "svec_base_regs.svh"

--- a/hdl/testbench/golden/run.do
+++ b/hdl/testbench/golden/run.do
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 vsim -quiet -t 10fs -L unisim work.main

 set StdArithNoWarnings 1

--- a/hdl/testbench/include/svec_base_regs.svh
+++ b/hdl/testbench/include/svec_base_regs.svh
+// SPDX-FileCopyrightText: 2022 CERN (home.cern)
+//
+// SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 package svec_base_regs_Consts;
  localparam SVEC_BASE_REGS_SIZE = 16384;
  localparam ADDR_SVEC_BASE_REGS_METADATA = 'h0;

--- a/software/kernel/.gitignore
+++ b/software/kernel/.gitignore
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 Makefile.specific
 svec-core-fpga.h
\ No newline at end of file
--- a/software/tools/.gitignore
+++ b/software/tools/.gitignore
 # SPDX-FileCopyrightText: 2021 CERN (home.cern)
 #
-# SPDX-License-Identifier: CC0-1.0
+# SPDX-License-Identifier: LGPL-2.1-or-later

 svec-firmware-version
\ No newline at end of file