Commit aa1ec6f4 authored by Tristan Gingold's avatar Tristan Gingold Committed by Federico Vaga

Add data pages for DMA (so that it supports MBLT).

The memory map of the svec base is therefore changed.
parent 88e02d16
memory-map: memory-map:
name: svec_base_regs name: svec_base_regs
bus: wb-32-be bus: wb-32-be
size: 0x2000 size: 0x4000
children: children:
- submap: - submap:
name: metadata name: metadata
...@@ -74,17 +74,6 @@ memory-map: ...@@ -74,17 +74,6 @@ memory-map:
x-hdl: x-hdl:
type: wire type: wire
write-strobe: True write-strobe: True
- reg:
name: ddr4_data
description: data to read or to write in ddr4
access: rw
width: 32
x-hdl:
type: wire
read-strobe: True
write-strobe: True
read-ack: True
write-ack: True
- reg: - reg:
name: ddr5_addr name: ddr5_addr
description: address of data to read or to write description: address of data to read or to write
...@@ -93,17 +82,6 @@ memory-map: ...@@ -93,17 +82,6 @@ memory-map:
x-hdl: x-hdl:
type: wire type: wire
write-strobe: True write-strobe: True
- reg:
name: ddr5_data
description: data to read or to write in ddr5
access: rw
width: 32
x-hdl:
type: wire
read-strobe: True
write-strobe: True
read-ack: True
write-ack: True
- submap: - submap:
name: therm_id name: therm_id
description: Thermometer and unique id description: Thermometer and unique id
...@@ -139,6 +117,7 @@ memory-map: ...@@ -139,6 +117,7 @@ memory-map:
- submap: - submap:
name: buildinfo name: buildinfo
description: a ROM containing build information description: a ROM containing build information
address: 0x200
size: 0x100 size: 0x100
interface: sram interface: sram
- submap: - submap:
...@@ -146,6 +125,22 @@ memory-map: ...@@ -146,6 +125,22 @@ memory-map:
address: 0x1000 address: 0x1000
description: white-rabbit core registers description: white-rabbit core registers
comment: In particular, the vuart is at 0x1500 comment: In particular, the vuart is at 0x1500
size: 0x800
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: ddr4_data
description: DMA page for ddr4
address: 0x2000
size: 0x1000
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: ddr5_data
description: DMA page for ddr5
address: 0x3000
size: 0x1000 size: 0x1000
interface: wb-32-be interface: wb-32-be
x-hdl: x-hdl:
......
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...@@ -234,15 +234,15 @@ TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk"; ...@@ -234,15 +234,15 @@ TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs"; NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMESPEC TS_ref_sync_ffs = FROM ref_clk TO "sys_sync_ffs" TIG; #TIMESPEC TS_ref_sync_ffs = FROM ref_clk TO "sys_sync_ffs" TIG;
TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG; #TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register # Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg"; NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
TIMEGRP "ref_sync_reg" = "sync_reg" EXCEPT "ref_clk"; #TIMEGRP "ref_sync_reg" = "sync_reg" EXCEPT "ref_clk";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk"; #TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "ref_sync_reg" 8ns DATAPATHONLY; #TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "ref_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg" 16ns DATAPATHONLY; #TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg" 16ns DATAPATHONLY;
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