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Simple VME FMC Carrier SVEC
Commit aa1ec6f4 authored by Tristan Gingold's avatar Tristan Gingold Committed by Federico Vaga
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Add data pages for DMA (so that it supports MBLT). 

The memory map of the svec base is therefore changed.
parent 88e02d16
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Showing with 471 additions and 492 deletions
hdl/rtl/svec_base_regs.cheby
View file @ aa1ec6f4
memory-map:
name: svec_base_regs
bus: wb-32-be
size: 0x2000
size: 0x4000
children:
- submap:
name: metadata
......@@ -74,17 +74,6 @@ memory-map:
x-hdl:
type: wire
write-strobe: True
- reg:
name: ddr4_data
description: data to read or to write in ddr4
access: rw
width: 32
x-hdl:
type: wire
read-strobe: True
write-strobe: True
read-ack: True
write-ack: True
- reg:
name: ddr5_addr
description: address of data to read or to write
......@@ -93,17 +82,6 @@ memory-map:
x-hdl:
type: wire
write-strobe: True
- reg:
name: ddr5_data
description: data to read or to write in ddr5
access: rw
width: 32
x-hdl:
type: wire
read-strobe: True
write-strobe: True
read-ack: True
write-ack: True
- submap:
name: therm_id
description: Thermometer and unique id
......@@ -139,6 +117,7 @@ memory-map:
- submap:
name: buildinfo
description: a ROM containing build information
address: 0x200
size: 0x100
interface: sram
- submap:
......@@ -146,6 +125,22 @@ memory-map:
address: 0x1000
description: white-rabbit core registers
comment: In particular, the vuart is at 0x1500
size: 0x800
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: ddr4_data
description: DMA page for ddr4
address: 0x2000
size: 0x1000
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: ddr5_data
description: DMA page for ddr5
address: 0x3000
size: 0x1000
interface: wb-32-be
x-hdl:
......
hdl/rtl/svec_base_regs.vhd
View file @ aa1ec6f4
-- Do not edit; this file was generated by Cheby using these options:
-- Do not edit. Generated on Fri Jan 29 13:36:51 2021 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- --gen-hdl=svec_base_regs.vhd -i svec_base_regs.cheby
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......@@ -12,7 +14,7 @@ entity svec_base_regs is
clk_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_adr_i : in std_logic_vector(12 downto 2);
wb_adr_i : in std_logic_vector(13 downto 2);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_dat_i : in std_logic_vector(31 downto 0);
......@@ -22,7 +24,7 @@ entity svec_base_regs is
wb_stall_o : out std_logic;
wb_dat_o : out std_logic_vector(31 downto 0);
-- a ROM containing the carrier metadata
-- SRAM bus metadata
metadata_addr_o : out std_logic_vector(5 downto 2);
metadata_data_i : in std_logic_vector(31 downto 0);
metadata_data_o : out std_logic_vector(31 downto 0);
......@@ -30,17 +32,21 @@ entity svec_base_regs is
-- offset to the application metadata
csr_app_offset_i : in std_logic_vector(31 downto 0);
-- global and application resets
csr_resets_global_o : out std_logic;
csr_resets_appl_o : out std_logic;
-- presence lines for the fmcs
csr_fmc_presence_i : in std_logic_vector(31 downto 0);
-- status of the ddr controllers
-- Set when ddr4 calibration is done.
csr_ddr_status_ddr4_calib_done_i : in std_logic;
-- Set when ddr5 calibration is done.
csr_ddr_status_ddr5_calib_done_i : in std_logic;
-- pcb revision
csr_pcb_rev_rev_i : in std_logic_vector(4 downto 0);
-- address of data to read or to write
......@@ -48,27 +54,11 @@ entity svec_base_regs is
csr_ddr4_addr_o : out std_logic_vector(31 downto 0);
csr_ddr4_addr_wr_o : out std_logic;
-- data to read or to write in ddr4
csr_ddr4_data_i : in std_logic_vector(31 downto 0);
csr_ddr4_data_o : out std_logic_vector(31 downto 0);
csr_ddr4_data_wr_o : out std_logic;
csr_ddr4_data_rd_o : out std_logic;
csr_ddr4_data_wack_i : in std_logic;
csr_ddr4_data_rack_i : in std_logic;
-- address of data to read or to write
csr_ddr5_addr_i : in std_logic_vector(31 downto 0);
csr_ddr5_addr_o : out std_logic_vector(31 downto 0);
csr_ddr5_addr_wr_o : out std_logic;
-- data to read or to write in ddr5
csr_ddr5_data_i : in std_logic_vector(31 downto 0);
csr_ddr5_data_o : out std_logic_vector(31 downto 0);
csr_ddr5_data_wr_o : out std_logic;
csr_ddr5_data_rd_o : out std_logic;
csr_ddr5_data_wack_i : in std_logic;
csr_ddr5_data_rack_i : in std_logic;
-- Thermometer and unique id
therm_id_i : in t_wishbone_master_in;
therm_id_o : out t_wishbone_master_out;
......@@ -85,21 +75,29 @@ entity svec_base_regs is
vic_i : in t_wishbone_master_in;
vic_o : out t_wishbone_master_out;
-- a ROM containing build information
-- SRAM bus buildinfo
buildinfo_addr_o : out std_logic_vector(7 downto 2);
buildinfo_data_i : in std_logic_vector(31 downto 0);
buildinfo_data_o : out std_logic_vector(31 downto 0);
buildinfo_wr_o : out std_logic;
-- white-rabbit core registers
-- In particular, the vuart is at 0x1500
wrc_regs_i : in t_wishbone_master_in;
wrc_regs_o : out t_wishbone_master_out
wrc_regs_o : out t_wishbone_master_out;
-- DMA page for ddr4
ddr4_data_i : in t_wishbone_master_in;
ddr4_data_o : out t_wishbone_master_out;
-- DMA page for ddr5
ddr5_data_i : in t_wishbone_master_in;
ddr5_data_o : out t_wishbone_master_out
);
end svec_base_regs;
architecture syn of svec_base_regs is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
......@@ -110,25 +108,33 @@ architecture syn of svec_base_regs is
signal metadata_re : std_logic;
signal csr_resets_global_reg : std_logic;
signal csr_resets_appl_reg : std_logic;
signal csr_resets_wreq : std_logic;
signal csr_resets_wack : std_logic;
signal csr_ddr4_addr_wreq : std_logic;
signal csr_ddr5_addr_wreq : std_logic;
signal therm_id_re : std_logic;
signal therm_id_we : std_logic;
signal therm_id_wt : std_logic;
signal therm_id_rt : std_logic;
signal therm_id_tr : std_logic;
signal therm_id_wack : std_logic;
signal therm_id_rack : std_logic;
signal fmc_i2c_re : std_logic;
signal fmc_i2c_we : std_logic;
signal fmc_i2c_wt : std_logic;
signal fmc_i2c_rt : std_logic;
signal fmc_i2c_tr : std_logic;
signal fmc_i2c_wack : std_logic;
signal fmc_i2c_rack : std_logic;
signal flash_spi_re : std_logic;
signal flash_spi_we : std_logic;
signal flash_spi_wt : std_logic;
signal flash_spi_rt : std_logic;
signal flash_spi_tr : std_logic;
signal flash_spi_wack : std_logic;
signal flash_spi_rack : std_logic;
signal vic_re : std_logic;
signal vic_we : std_logic;
signal vic_wt : std_logic;
signal vic_rt : std_logic;
signal vic_tr : std_logic;
......@@ -137,13 +143,36 @@ architecture syn of svec_base_regs is
signal buildinfo_rack : std_logic;
signal buildinfo_re : std_logic;
signal wrc_regs_re : std_logic;
signal wrc_regs_we : std_logic;
signal wrc_regs_wt : std_logic;
signal wrc_regs_rt : std_logic;
signal wrc_regs_tr : std_logic;
signal wrc_regs_wack : std_logic;
signal wrc_regs_rack : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
signal ddr4_data_re : std_logic;
signal ddr4_data_we : std_logic;
signal ddr4_data_wt : std_logic;
signal ddr4_data_rt : std_logic;
signal ddr4_data_tr : std_logic;
signal ddr4_data_wack : std_logic;
signal ddr4_data_rack : std_logic;
signal ddr5_data_re : std_logic;
signal ddr5_data_we : std_logic;
signal ddr5_data_wt : std_logic;
signal ddr5_data_rt : std_logic;
signal ddr5_data_tr : std_logic;
signal ddr5_data_wack : std_logic;
signal ddr5_data_rack : std_logic;
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_adr_d0 : std_logic_vector(13 downto 2);
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
signal metadata_wp : std_logic;
signal metadata_we : std_logic;
signal buildinfo_wp : std_logic;
signal buildinfo_we : std_logic;
begin
-- WB decode signals
......@@ -158,7 +187,7 @@ begin
end if;
end if;
end process;
rd_int <= (wb_en and not wb_we_i) and not wb_rip;
rd_req_int <= (wb_en and not wb_we_i) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
......@@ -169,7 +198,7 @@ begin
end if;
end if;
end process;
wr_int <= (wb_en and wb_we_i) and not wb_wip;
wr_req_int <= (wb_en and wb_we_i) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_ack_o <= ack_int;
......@@ -177,7 +206,24 @@ begin
wb_rty_o <= '0';
wb_err_o <= '0';
-- Assign outputs
-- pipelining for wr-in+rd-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wr_req_d0 <= '0';
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_adr_d0 <= wb_adr_i;
wr_dat_d0 <= wb_dat_i;
wr_sel_d0 <= wb_sel_i;
end if;
end if;
end process;
-- Interface metadata
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
......@@ -187,19 +233,72 @@ begin
end if;
end if;
end process;
metadata_data_o <= wb_dat_i;
metadata_addr_o <= wb_adr_i(5 downto 2);
metadata_data_o <= wr_dat_d0;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_wp <= '0';
else
metadata_wp <= (wr_req_d0 or metadata_wp) and rd_req_int;
end if;
end if;
end process;
metadata_we <= (wr_req_d0 or metadata_wp) and not rd_req_int;
process (wb_adr_i, wr_adr_d0, metadata_re) begin
if metadata_re = '1' then
metadata_addr_o <= wb_adr_i(5 downto 2);
else
metadata_addr_o <= wr_adr_d0(5 downto 2);
end if;
end process;
-- Register csr_app_offset
-- Register csr_resets
csr_resets_global_o <= csr_resets_global_reg;
csr_resets_appl_o <= csr_resets_appl_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
csr_resets_global_reg <= '0';
csr_resets_appl_reg <= '0';
csr_resets_wack <= '0';
else
if csr_resets_wreq = '1' then
csr_resets_global_reg <= wr_dat_d0(0);
csr_resets_appl_reg <= wr_dat_d0(1);
end if;
csr_resets_wack <= csr_resets_wreq;
end if;
end if;
end process;
-- Assignments for submap therm_id
-- Register csr_fmc_presence
-- Register csr_unused0
-- Register csr_ddr_status
-- Register csr_pcb_rev
-- Register csr_ddr4_addr
csr_ddr4_addr_o <= wr_dat_d0;
csr_ddr4_addr_wr_o <= csr_ddr4_addr_wreq;
-- Register csr_ddr5_addr
csr_ddr5_addr_o <= wr_dat_d0;
csr_ddr5_addr_wr_o <= csr_ddr5_addr_wreq;
-- Interface therm_id
therm_id_tr <= therm_id_wt or therm_id_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
therm_id_rt <= '0';
therm_id_wt <= '0';
else
therm_id_rt <= (therm_id_rt or therm_id_re) and not therm_id_rack;
therm_id_wt <= (therm_id_wt or therm_id_we) and not therm_id_wack;
end if;
end if;
end process;
......@@ -208,18 +307,20 @@ begin
therm_id_wack <= therm_id_i.ack and therm_id_wt;
therm_id_rack <= therm_id_i.ack and therm_id_rt;
therm_id_o.adr <= ((27 downto 0 => '0') & wb_adr_i(3 downto 2)) & (1 downto 0 => '0');
therm_id_o.sel <= (others => '1');
therm_id_o.sel <= wr_sel_d0;
therm_id_o.we <= therm_id_wt;
therm_id_o.dat <= wb_dat_i;
therm_id_o.dat <= wr_dat_d0;
-- Assignments for submap fmc_i2c
-- Interface fmc_i2c
fmc_i2c_tr <= fmc_i2c_wt or fmc_i2c_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc_i2c_rt <= '0';
fmc_i2c_wt <= '0';
else
fmc_i2c_rt <= (fmc_i2c_rt or fmc_i2c_re) and not fmc_i2c_rack;
fmc_i2c_wt <= (fmc_i2c_wt or fmc_i2c_we) and not fmc_i2c_wack;
end if;
end if;
end process;
......@@ -228,18 +329,20 @@ begin
fmc_i2c_wack <= fmc_i2c_i.ack and fmc_i2c_wt;
fmc_i2c_rack <= fmc_i2c_i.ack and fmc_i2c_rt;
fmc_i2c_o.adr <= ((26 downto 0 => '0') & wb_adr_i(4 downto 2)) & (1 downto 0 => '0');
fmc_i2c_o.sel <= (others => '1');
fmc_i2c_o.sel <= wr_sel_d0;
fmc_i2c_o.we <= fmc_i2c_wt;
fmc_i2c_o.dat <= wb_dat_i;
fmc_i2c_o.dat <= wr_dat_d0;
-- Assignments for submap flash_spi
-- Interface flash_spi
flash_spi_tr <= flash_spi_wt or flash_spi_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
flash_spi_rt <= '0';
flash_spi_wt <= '0';
else
flash_spi_rt <= (flash_spi_rt or flash_spi_re) and not flash_spi_rack;
flash_spi_wt <= (flash_spi_wt or flash_spi_we) and not flash_spi_wack;
end if;
end if;
end process;
......@@ -248,18 +351,20 @@ begin
flash_spi_wack <= flash_spi_i.ack and flash_spi_wt;
flash_spi_rack <= flash_spi_i.ack and flash_spi_rt;
flash_spi_o.adr <= ((26 downto 0 => '0') & wb_adr_i(4 downto 2)) & (1 downto 0 => '0');
flash_spi_o.sel <= (others => '1');
flash_spi_o.sel <= wr_sel_d0;
flash_spi_o.we <= flash_spi_wt;
flash_spi_o.dat <= wb_dat_i;
flash_spi_o.dat <= wr_dat_d0;
-- Assignments for submap vic
-- Interface vic
vic_tr <= vic_wt or vic_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
vic_rt <= '0';
vic_wt <= '0';
else
vic_rt <= (vic_rt or vic_re) and not vic_rack;
vic_wt <= (vic_wt or vic_we) and not vic_wack;
end if;
end if;
end process;
......@@ -268,9 +373,11 @@ begin
vic_wack <= vic_i.ack and vic_wt;
vic_rack <= vic_i.ack and vic_rt;
vic_o.adr <= ((23 downto 0 => '0') & wb_adr_i(7 downto 2)) & (1 downto 0 => '0');
vic_o.sel <= (others => '1');
vic_o.sel <= wr_sel_d0;
vic_o.we <= vic_wt;
vic_o.dat <= wb_dat_i;
vic_o.dat <= wr_dat_d0;
-- Interface buildinfo
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
......@@ -280,17 +387,35 @@ begin
end if;
end if;
end process;
buildinfo_data_o <= wb_dat_i;
buildinfo_addr_o <= wb_adr_i(7 downto 2);
buildinfo_data_o <= wr_dat_d0;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
buildinfo_wp <= '0';
else
buildinfo_wp <= (wr_req_d0 or buildinfo_wp) and rd_req_int;
end if;
end if;
end process;
buildinfo_we <= (wr_req_d0 or buildinfo_wp) and not rd_req_int;
process (wb_adr_i, wr_adr_d0, buildinfo_re) begin
if buildinfo_re = '1' then
buildinfo_addr_o <= wb_adr_i(7 downto 2);
else
buildinfo_addr_o <= wr_adr_d0(7 downto 2);
end if;
end process;
-- Assignments for submap wrc_regs
-- Interface wrc_regs
wrc_regs_tr <= wrc_regs_wt or wrc_regs_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wrc_regs_rt <= '0';
wrc_regs_wt <= '0';
else
wrc_regs_rt <= (wrc_regs_rt or wrc_regs_re) and not wrc_regs_rack;
wrc_regs_wt <= (wrc_regs_wt or wrc_regs_we) and not wrc_regs_wack;
end if;
end if;
end process;
......@@ -298,242 +423,162 @@ begin
wrc_regs_o.stb <= wrc_regs_tr;
wrc_regs_wack <= wrc_regs_i.ack and wrc_regs_wt;
wrc_regs_rack <= wrc_regs_i.ack and wrc_regs_rt;
wrc_regs_o.adr <= ((19 downto 0 => '0') & wb_adr_i(11 downto 2)) & (1 downto 0 => '0');
wrc_regs_o.sel <= (others => '1');
wrc_regs_o.adr <= ((20 downto 0 => '0') & wb_adr_i(10 downto 2)) & (1 downto 0 => '0');
wrc_regs_o.sel <= wr_sel_d0;
wrc_regs_o.we <= wrc_regs_wt;
wrc_regs_o.dat <= wb_dat_i;
wrc_regs_o.dat <= wr_dat_d0;
-- Process for write requests.
-- Interface ddr4_data
ddr4_data_tr <= ddr4_data_wt or ddr4_data_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
metadata_wr_o <= '0';
csr_resets_global_reg <= '0';
csr_resets_appl_reg <= '0';
csr_ddr4_addr_wr_o <= '0';
csr_ddr4_data_wr_o <= '0';
csr_ddr5_addr_wr_o <= '0';
csr_ddr5_data_wr_o <= '0';
therm_id_wt <= '0';
fmc_i2c_wt <= '0';
flash_spi_wt <= '0';
vic_wt <= '0';
buildinfo_wr_o <= '0';
wrc_regs_wt <= '0';
ddr4_data_rt <= '0';
ddr4_data_wt <= '0';
else
wr_ack_int <= '0';
metadata_wr_o <= '0';
csr_ddr4_addr_wr_o <= '0';
csr_ddr4_data_wr_o <= '0';
csr_ddr5_addr_wr_o <= '0';
csr_ddr5_data_wr_o <= '0';
therm_id_wt <= '0';
fmc_i2c_wt <= '0';
flash_spi_wt <= '0';
vic_wt <= '0';
buildinfo_wr_o <= '0';
wrc_regs_wt <= '0';
case wb_adr_i(12 downto 12) is
when "0" =>
case wb_adr_i(11 downto 8) is
when "0000" =>
case wb_adr_i(7 downto 6) is
when "00" =>
-- Submap metadata
metadata_wr_o <= wr_int;
wr_ack_int <= wr_int;
when "01" =>
case wb_adr_i(5 downto 2) is
when "0000" =>
-- Register csr_app_offset
when "0001" =>
-- Register csr_resets
if wr_int = '1' then
csr_resets_global_reg <= wb_dat_i(0);
csr_resets_appl_reg <= wb_dat_i(1);
end if;
wr_ack_int <= wr_int;
when "0010" =>
-- Register csr_fmc_presence
when "0011" =>
-- Register csr_unused0
when "0100" =>
-- Register csr_ddr_status
when "0101" =>
-- Register csr_pcb_rev
when "0110" =>
-- Register csr_ddr4_addr
csr_ddr4_addr_wr_o <= wr_int;
if wr_int = '1' then
csr_ddr4_addr_o <= wb_dat_i;
end if;
wr_ack_int <= wr_int;
when "0111" =>
-- Register csr_ddr4_data
csr_ddr4_data_wr_o <= wr_int;
if wr_int = '1' then
csr_ddr4_data_o <= wb_dat_i;
end if;
wr_ack_int <= csr_ddr4_data_wack_i;
when "1000" =>
-- Register csr_ddr5_addr
csr_ddr5_addr_wr_o <= wr_int;
if wr_int = '1' then
csr_ddr5_addr_o <= wb_dat_i;
end if;
wr_ack_int <= wr_int;
when "1001" =>
-- Register csr_ddr5_data
csr_ddr5_data_wr_o <= wr_int;
if wr_int = '1' then
csr_ddr5_data_o <= wb_dat_i;
end if;
wr_ack_int <= csr_ddr5_data_wack_i;
when others =>
wr_ack_int <= wr_int;
end case;
when "10" =>
case wb_adr_i(5 downto 5) is
when "0" =>
-- Submap therm_id
therm_id_wt <= (therm_id_wt or wr_int) and not therm_id_wack;
wr_ack_int <= therm_id_wack;
when "1" =>
-- Submap fmc_i2c
fmc_i2c_wt <= (fmc_i2c_wt or wr_int) and not fmc_i2c_wack;
wr_ack_int <= fmc_i2c_wack;
when others =>
wr_ack_int <= wr_int;
end case;
when "11" =>
-- Submap flash_spi
flash_spi_wt <= (flash_spi_wt or wr_int) and not flash_spi_wack;
wr_ack_int <= flash_spi_wack;
when others =>
wr_ack_int <= wr_int;
end case;
when "0001" =>
-- Submap vic
vic_wt <= (vic_wt or wr_int) and not vic_wack;
wr_ack_int <= vic_wack;
when "0010" =>
-- Submap buildinfo
buildinfo_wr_o <= wr_int;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= wr_int;
end case;
when "1" =>
-- Submap wrc_regs
wrc_regs_wt <= (wrc_regs_wt or wr_int) and not wrc_regs_wack;
wr_ack_int <= wrc_regs_wack;
when others =>
wr_ack_int <= wr_int;
end case;
ddr4_data_rt <= (ddr4_data_rt or ddr4_data_re) and not ddr4_data_rack;
ddr4_data_wt <= (ddr4_data_wt or ddr4_data_we) and not ddr4_data_wack;
end if;
end if;
end process;
ddr4_data_o.cyc <= ddr4_data_tr;
ddr4_data_o.stb <= ddr4_data_tr;
ddr4_data_wack <= ddr4_data_i.ack and ddr4_data_wt;
ddr4_data_rack <= ddr4_data_i.ack and ddr4_data_rt;
ddr4_data_o.adr <= ((19 downto 0 => '0') & wb_adr_i(11 downto 2)) & (1 downto 0 => '0');
ddr4_data_o.sel <= wr_sel_d0;
ddr4_data_o.we <= ddr4_data_wt;
ddr4_data_o.dat <= wr_dat_d0;
-- Process for registers read.
-- Interface ddr5_data
ddr5_data_tr <= ddr5_data_wt or ddr5_data_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
csr_ddr4_data_rd_o <= '0';
csr_ddr5_data_rd_o <= '0';
ddr5_data_rt <= '0';
ddr5_data_wt <= '0';
else
csr_ddr5_data_rd_o <= '0';
csr_ddr4_data_rd_o <= '0';
reg_rdat_int <= (others => '0');
case wb_adr_i(12 downto 12) is
when "0" =>
case wb_adr_i(11 downto 8) is
when "0000" =>
case wb_adr_i(7 downto 6) is
when "00" =>
when "01" =>
case wb_adr_i(5 downto 2) is
when "0000" =>
-- csr_app_offset
reg_rdat_int <= csr_app_offset_i;
rd_ack1_int <= rd_int;
when "0001" =>
-- csr_resets
reg_rdat_int(0) <= csr_resets_global_reg;
reg_rdat_int(1) <= csr_resets_appl_reg;
rd_ack1_int <= rd_int;
when "0010" =>
-- csr_fmc_presence
reg_rdat_int <= csr_fmc_presence_i;
rd_ack1_int <= rd_int;
when "0011" =>
-- csr_unused0
reg_rdat_int <= "00000000000000000000000000000000";
rd_ack1_int <= rd_int;
when "0100" =>
-- csr_ddr_status
reg_rdat_int(0) <= csr_ddr_status_ddr4_calib_done_i;
reg_rdat_int(1) <= csr_ddr_status_ddr5_calib_done_i;
rd_ack1_int <= rd_int;
when "0101" =>
-- csr_pcb_rev
reg_rdat_int(4 downto 0) <= csr_pcb_rev_rev_i;
rd_ack1_int <= rd_int;
when "0110" =>
-- csr_ddr4_addr
reg_rdat_int <= csr_ddr4_addr_i;
rd_ack1_int <= rd_int;
when "0111" =>
-- csr_ddr4_data
reg_rdat_int <= csr_ddr4_data_i;
csr_ddr4_data_rd_o <= rd_int;
rd_ack1_int <= csr_ddr4_data_rack_i;
when "1000" =>
-- csr_ddr5_addr
reg_rdat_int <= csr_ddr5_addr_i;
rd_ack1_int <= rd_int;
when "1001" =>
-- csr_ddr5_data
reg_rdat_int <= csr_ddr5_data_i;
csr_ddr5_data_rd_o <= rd_int;
rd_ack1_int <= csr_ddr5_data_rack_i;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "10" =>
case wb_adr_i(5 downto 5) is
when "0" =>
when "1" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "11" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "0001" =>
when "0010" =>
ddr5_data_rt <= (ddr5_data_rt or ddr5_data_re) and not ddr5_data_rack;
ddr5_data_wt <= (ddr5_data_wt or ddr5_data_we) and not ddr5_data_wack;
end if;
end if;
end process;
ddr5_data_o.cyc <= ddr5_data_tr;
ddr5_data_o.stb <= ddr5_data_tr;
ddr5_data_wack <= ddr5_data_i.ack and ddr5_data_wt;
ddr5_data_rack <= ddr5_data_i.ack and ddr5_data_rt;
ddr5_data_o.adr <= ((19 downto 0 => '0') & wb_adr_i(11 downto 2)) & (1 downto 0 => '0');
ddr5_data_o.sel <= wr_sel_d0;
ddr5_data_o.we <= ddr5_data_wt;
ddr5_data_o.dat <= wr_dat_d0;
-- Process for write requests.
process (wr_adr_d0, metadata_we, wr_req_d0, csr_resets_wack, therm_id_wack, fmc_i2c_wack, flash_spi_wack, vic_wack, buildinfo_we, wrc_regs_wack, ddr4_data_wack, ddr5_data_wack) begin
metadata_wr_o <= '0';
csr_resets_wreq <= '0';
csr_ddr4_addr_wreq <= '0';
csr_ddr5_addr_wreq <= '0';
therm_id_we <= '0';
fmc_i2c_we <= '0';
flash_spi_we <= '0';
vic_we <= '0';
buildinfo_wr_o <= '0';
wrc_regs_we <= '0';
ddr4_data_we <= '0';
ddr5_data_we <= '0';
case wr_adr_d0(13 downto 12) is
when "00" =>
case wr_adr_d0(11 downto 8) is
when "0000" =>
case wr_adr_d0(7 downto 6) is
when "00" =>
-- Submap metadata
metadata_wr_o <= metadata_we;
wr_ack_int <= metadata_we;
when "01" =>
case wr_adr_d0(5 downto 2) is
when "0000" =>
-- Reg csr_app_offset
wr_ack_int <= wr_req_d0;
when "0001" =>
-- Reg csr_resets
csr_resets_wreq <= wr_req_d0;
wr_ack_int <= csr_resets_wack;
when "0010" =>
-- Reg csr_fmc_presence
wr_ack_int <= wr_req_d0;
when "0011" =>
-- Reg csr_unused0
wr_ack_int <= wr_req_d0;
when "0100" =>
-- Reg csr_ddr_status
wr_ack_int <= wr_req_d0;
when "0101" =>
-- Reg csr_pcb_rev
wr_ack_int <= wr_req_d0;
when "0110" =>
-- Reg csr_ddr4_addr
csr_ddr4_addr_wreq <= wr_req_d0;
wr_ack_int <= wr_req_d0;
when "0111" =>
-- Reg csr_ddr5_addr
csr_ddr5_addr_wreq <= wr_req_d0;
wr_ack_int <= wr_req_d0;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
wr_ack_int <= wr_req_d0;
end case;
when "1" =>
when "10" =>
case wr_adr_d0(5 downto 5) is
when "0" =>
-- Submap therm_id
therm_id_we <= wr_req_d0;
wr_ack_int <= therm_id_wack;
when "1" =>
-- Submap fmc_i2c
fmc_i2c_we <= wr_req_d0;
wr_ack_int <= fmc_i2c_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "11" =>
-- Submap flash_spi
flash_spi_we <= wr_req_d0;
wr_ack_int <= flash_spi_wack;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
wr_ack_int <= wr_req_d0;
end case;
end if;
end if;
when "0001" =>
-- Submap vic
vic_we <= wr_req_d0;
wr_ack_int <= vic_wack;
when "0010" =>
-- Submap buildinfo
buildinfo_wr_o <= buildinfo_we;
wr_ack_int <= buildinfo_we;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "01" =>
-- Submap wrc_regs
wrc_regs_we <= wr_req_d0;
wr_ack_int <= wrc_regs_wack;
when "10" =>
-- Submap ddr4_data
ddr4_data_we <= wr_req_d0;
wr_ack_int <= ddr4_data_wack;
when "11" =>
-- Submap ddr5_data
ddr5_data_we <= wr_req_d0;
wr_ack_int <= ddr5_data_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (wb_adr_i, reg_rdat_int, rd_ack1_int, rd_int, rd_int, metadata_data_i, metadata_rack, rd_int, therm_id_i.dat, therm_id_rack, therm_id_rt, rd_int, fmc_i2c_i.dat, fmc_i2c_rack, fmc_i2c_rt, rd_int, flash_spi_i.dat, flash_spi_rack, flash_spi_rt, rd_int, vic_i.dat, vic_rack, vic_rt, rd_int, buildinfo_data_i, buildinfo_rack, rd_int, wrc_regs_i.dat, wrc_regs_rack, wrc_regs_rt) begin
process (wb_adr_i, metadata_data_i, metadata_rack, rd_req_int, csr_app_offset_i, csr_resets_global_reg, csr_resets_appl_reg, csr_fmc_presence_i, csr_ddr_status_ddr4_calib_done_i, csr_ddr_status_ddr5_calib_done_i, csr_pcb_rev_rev_i, csr_ddr4_addr_i, csr_ddr5_addr_i, therm_id_i.dat, therm_id_rack, fmc_i2c_i.dat, fmc_i2c_rack, flash_spi_i.dat, flash_spi_rack, vic_i.dat, vic_rack, buildinfo_data_i, buildinfo_rack, wrc_regs_i.dat, wrc_regs_rack, ddr4_data_i.dat, ddr4_data_rack, ddr5_data_i.dat, ddr5_data_rack) begin
-- By default ack read requests
wb_dat_o <= (others => '0');
rd_dat_d0 <= (others => 'X');
metadata_re <= '0';
therm_id_re <= '0';
fmc_i2c_re <= '0';
......@@ -541,104 +586,113 @@ begin
vic_re <= '0';
buildinfo_re <= '0';
wrc_regs_re <= '0';
case wb_adr_i(12 downto 12) is
when "0" =>
ddr4_data_re <= '0';
ddr5_data_re <= '0';
case wb_adr_i(13 downto 12) is
when "00" =>
case wb_adr_i(11 downto 8) is
when "0000" =>
when "0000" =>
case wb_adr_i(7 downto 6) is
when "00" =>
when "00" =>
-- Submap metadata
wb_dat_o <= metadata_data_i;
rd_ack_int <= metadata_rack;
metadata_re <= rd_int;
when "01" =>
rd_dat_d0 <= metadata_data_i;
rd_ack_d0 <= metadata_rack;
metadata_re <= rd_req_int;
when "01" =>
case wb_adr_i(5 downto 2) is
when "0000" =>
-- csr_app_offset
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "0001" =>
-- csr_resets
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "0010" =>
-- csr_fmc_presence
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "0011" =>
-- csr_unused0
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "0100" =>
-- csr_ddr_status
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "0101" =>
-- csr_pcb_rev
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "0110" =>
-- csr_ddr4_addr
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "0111" =>
-- csr_ddr4_data
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "1000" =>
-- csr_ddr5_addr
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "1001" =>
-- csr_ddr5_data
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "0000" =>
-- Reg csr_app_offset
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= csr_app_offset_i;
when "0001" =>
-- Reg csr_resets
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= csr_resets_global_reg;
rd_dat_d0(1) <= csr_resets_appl_reg;
rd_dat_d0(31 downto 2) <= (others => '0');
when "0010" =>
-- Reg csr_fmc_presence
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= csr_fmc_presence_i;
when "0011" =>
-- Reg csr_unused0
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= "00000000000000000000000000000000";
when "0100" =>
-- Reg csr_ddr_status
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= csr_ddr_status_ddr4_calib_done_i;
rd_dat_d0(1) <= csr_ddr_status_ddr5_calib_done_i;
rd_dat_d0(31 downto 2) <= (others => '0');
when "0101" =>
-- Reg csr_pcb_rev
rd_ack_d0 <= rd_req_int;
rd_dat_d0(4 downto 0) <= csr_pcb_rev_rev_i;
rd_dat_d0(31 downto 5) <= (others => '0');
when "0110" =>
-- Reg csr_ddr4_addr
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= csr_ddr4_addr_i;
when "0111" =>
-- Reg csr_ddr5_addr
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= csr_ddr5_addr_i;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
when "10" =>
when "10" =>
case wb_adr_i(5 downto 5) is
when "0" =>
when "0" =>
-- Submap therm_id
therm_id_re <= rd_int;
wb_dat_o <= therm_id_i.dat;
rd_ack_int <= therm_id_rack;
when "1" =>
therm_id_re <= rd_req_int;
rd_dat_d0 <= therm_id_i.dat;
rd_ack_d0 <= therm_id_rack;
when "1" =>
-- Submap fmc_i2c
fmc_i2c_re <= rd_int;
wb_dat_o <= fmc_i2c_i.dat;
rd_ack_int <= fmc_i2c_rack;
fmc_i2c_re <= rd_req_int;
rd_dat_d0 <= fmc_i2c_i.dat;
rd_ack_d0 <= fmc_i2c_rack;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
when "11" =>
when "11" =>
-- Submap flash_spi
flash_spi_re <= rd_int;
wb_dat_o <= flash_spi_i.dat;
rd_ack_int <= flash_spi_rack;
flash_spi_re <= rd_req_int;
rd_dat_d0 <= flash_spi_i.dat;
rd_ack_d0 <= flash_spi_rack;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
when "0001" =>
when "0001" =>
-- Submap vic
vic_re <= rd_int;
wb_dat_o <= vic_i.dat;
rd_ack_int <= vic_rack;
when "0010" =>
vic_re <= rd_req_int;
rd_dat_d0 <= vic_i.dat;
rd_ack_d0 <= vic_rack;
when "0010" =>
-- Submap buildinfo
wb_dat_o <= buildinfo_data_i;
rd_ack_int <= buildinfo_rack;
buildinfo_re <= rd_int;
rd_dat_d0 <= buildinfo_data_i;
rd_ack_d0 <= buildinfo_rack;
buildinfo_re <= rd_req_int;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
when "1" =>
when "01" =>
-- Submap wrc_regs
wrc_regs_re <= rd_int;
wb_dat_o <= wrc_regs_i.dat;
rd_ack_int <= wrc_regs_rack;
wrc_regs_re <= rd_req_int;
rd_dat_d0 <= wrc_regs_i.dat;
rd_ack_d0 <= wrc_regs_rack;
when "10" =>
-- Submap ddr4_data
ddr4_data_re <= rd_req_int;
rd_dat_d0 <= ddr4_data_i.dat;
rd_ack_d0 <= ddr4_data_rack;
when "11" =>
-- Submap ddr5_data
ddr5_data_re <= rd_req_int;
rd_dat_d0 <= ddr5_data_i.dat;
rd_ack_d0 <= ddr5_data_rack;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
end process;
end syn;
hdl/rtl/svec_base_wr.vhd
View file @ aa1ec6f4
......@@ -359,19 +359,10 @@ architecture top of svec_base_wr is
signal csr_ddr4_addr : std_logic_vector(31 downto 0);
-- data to read or to write in ddr4
signal csr_ddr4_data_in : std_logic_vector(31 downto 0);
signal csr_ddr4_data_out : std_logic_vector(31 downto 0);
signal csr_ddr4_data_wr : std_logic;
signal csr_ddr4_data_rd : std_logic;
signal csr_ddr4_data_wack : std_logic;
signal csr_ddr4_data_rack : std_logic;
--
signal ddr4_read_ip : std_logic;
signal ddr4_write_ip : std_logic;
signal ddr4_wb_out : t_wishbone_master_out;
signal ddr4_wb_in : t_wishbone_master_in;
signal ddr4_data_in : t_wishbone_master_in;
signal ddr4_data_out : t_wishbone_master_out;
signal ddr4_data_stb_d : std_logic;
signal ddr4_data_stb : std_logic;
-- Address for ddr5.
signal csr_ddr5_addr_out : std_logic_vector(31 downto 0);
......@@ -379,19 +370,10 @@ architecture top of svec_base_wr is
signal csr_ddr5_addr : std_logic_vector(31 downto 0);
-- data to read or to write in ddr5
signal csr_ddr5_data_in : std_logic_vector(31 downto 0);
signal csr_ddr5_data_out : std_logic_vector(31 downto 0);
signal csr_ddr5_data_wr : std_logic;
signal csr_ddr5_data_rd : std_logic;
signal csr_ddr5_data_wack : std_logic;
signal csr_ddr5_data_rack : std_logic;
--
signal ddr5_read_ip : std_logic;
signal ddr5_write_ip : std_logic;
signal ddr5_wb_out : t_wishbone_master_out;
signal ddr5_wb_in : t_wishbone_master_in;
signal ddr5_data_in : t_wishbone_master_in;
signal ddr5_data_out : t_wishbone_master_out;
signal ddr5_data_stb_d : std_logic;
signal ddr5_data_stb : std_logic;
signal vme_wb_out : t_wishbone_master_out;
signal vme_wb_in : t_wishbone_master_in;
......@@ -545,7 +527,7 @@ begin -- architecture top
-- Mini-crossbar from vme to carrier and application bus.
inst_split: entity work.xwb_split
generic map (
g_mask => x"ffff_e000"
g_mask => x"ffff_c000"
)
port map (
clk_sys_i => clk_sys_62m5,
......@@ -558,13 +540,13 @@ begin -- architecture top
master_o (1) => app_wb_o
);
inst_carrier: entity work.svec_base_regs
inst_svec_base_regs: entity work.svec_base_regs
port map (
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
wb_cyc_i => carrier_wb_in.cyc,
wb_stb_i => carrier_wb_in.stb,
wb_adr_i => carrier_wb_in.adr (12 downto 2), -- Bytes address from vme64x core
wb_adr_i => carrier_wb_in.adr (13 downto 2), -- Bytes address from vme64x core
wb_sel_i => carrier_wb_in.sel,
wb_we_i => carrier_wb_in.we,
wb_dat_i => carrier_wb_in.dat,
......@@ -595,26 +577,10 @@ begin -- architecture top
csr_ddr4_addr_o => csr_ddr4_addr_out,
csr_ddr4_addr_wr_o => csr_ddr4_addr_wr,
-- data to read or to write in ddr4
csr_ddr4_data_i => csr_ddr4_data_in,
csr_ddr4_data_o => csr_ddr4_data_out,
csr_ddr4_data_wr_o => csr_ddr4_data_wr,
csr_ddr4_data_rd_o => csr_ddr4_data_rd,
csr_ddr4_data_wack_i => csr_ddr4_data_wack,
csr_ddr4_data_rack_i => csr_ddr4_data_rack,
csr_ddr5_addr_i => csr_ddr5_addr,
csr_ddr5_addr_o => csr_ddr5_addr_out,
csr_ddr5_addr_wr_o => csr_ddr5_addr_wr,
-- data to read or to write in ddr5
csr_ddr5_data_i => csr_ddr5_data_in,
csr_ddr5_data_o => csr_ddr5_data_out,
csr_ddr5_data_wr_o => csr_ddr5_data_wr,
csr_ddr5_data_rd_o => csr_ddr5_data_rd,
csr_ddr5_data_wack_i => csr_ddr5_data_wack,
csr_ddr5_data_rack_i => csr_ddr5_data_rack,
-- Thermometer and unique id
therm_id_i => therm_id_in,
therm_id_o => therm_id_out,
......@@ -638,7 +604,15 @@ begin -- architecture top
-- white-rabbit core
wrc_regs_i => wrc_in,
wrc_regs_o => wrc_out
wrc_regs_o => wrc_out,
-- data to read or to write in ddr4
ddr4_data_i => ddr4_data_in,
ddr4_data_o => ddr4_data_out,
-- data to read or to write in ddr5
ddr5_data_i => ddr5_data_in,
ddr5_data_o => ddr5_data_out
);
fmc_presence (0) <= not fmc0_prsnt_m2c_n_i;
......@@ -658,7 +632,7 @@ begin -- architecture top
metadata_data <= x"53564543";
when x"2" =>
-- Version
metadata_data <= x"01050002";
metadata_data <= x"02000001";
when x"3" =>
-- BOM
metadata_data <= x"fffe0000";
......@@ -1163,15 +1137,15 @@ begin -- architecture top
wb1_rst_n_i => rst_gbl_n,
wb1_clk_i => clk_sys_62m5,
wb1_sel_i => ddr4_wb_out.sel,
wb1_cyc_i => ddr4_wb_out.cyc,
wb1_stb_i => ddr4_wb_out.stb,
wb1_we_i => ddr4_wb_out.we,
wb1_addr_i => ddr4_wb_out.adr,
wb1_data_i => ddr4_wb_out.dat,
wb1_data_o => ddr4_wb_in.dat,
wb1_ack_o => ddr4_wb_in.ack,
wb1_stall_o => ddr4_wb_in.stall,
wb1_sel_i => ddr4_data_out.sel,
wb1_cyc_i => ddr4_data_out.cyc,
wb1_stb_i => ddr4_data_stb,
wb1_we_i => ddr4_data_out.we,
wb1_addr_i => csr_ddr4_addr,
wb1_data_i => ddr4_data_out.dat,
wb1_data_o => ddr4_data_in.dat,
wb1_ack_o => ddr4_data_in.ack,
wb1_stall_o => ddr4_data_in.stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
......@@ -1190,8 +1164,8 @@ begin -- architecture top
ddr4_calib_done <= ddr4_status(0);
-- unused Wishbone signals
ddr4_wb_in.err <= '0';
ddr4_wb_in.rty <= '0';
ddr4_data_in.err <= '0';
ddr4_data_in.rty <= '0';
p_ddr4_addr: process (clk_sys_62m5)
begin
......@@ -1200,39 +1174,19 @@ begin -- architecture top
csr_ddr4_addr <= x"0000_0000";
elsif csr_ddr4_addr_wr = '1' then
csr_ddr4_addr <= csr_ddr4_addr_out;
elsif ddr4_wb_in.ack = '1' then
elsif ddr4_data_in.ack = '1' then
csr_ddr4_addr <= std_logic_vector(unsigned(csr_ddr4_addr) + 4);
end if;
end if;
end process;
p_ddr4_ack: process (clk_sys_62m5)
begin
if rising_edge(clk_sys_62m5) then
if rst_sys_62m5_n = '0' then
ddr4_read_ip <= '0';
ddr4_write_ip <= '0';
else
ddr4_read_ip <= csr_ddr4_data_rd or (ddr4_read_ip and not ddr4_wb_in.ack);
ddr4_write_ip <= csr_ddr4_data_wr or (ddr4_write_ip and not ddr4_wb_in.ack);
end if;
ddr4_data_stb_d <= ddr4_data_out.stb;
end if;
end process;
ddr4_wb_out <= (adr => csr_ddr4_addr,
cyc => csr_ddr4_data_rd or csr_ddr4_data_wr or ddr4_read_ip or ddr4_write_ip,
stb => csr_ddr4_data_rd or csr_ddr4_data_wr,
sel => x"f",
we => csr_ddr4_data_wr,
dat => csr_ddr4_data_out);
csr_ddr4_data_in <= ddr4_wb_in.dat;
csr_ddr4_data_rack <= ddr4_read_ip and ddr4_wb_in.ack;
csr_ddr4_data_wack <= ddr4_write_ip and ddr4_wb_in.ack;
ddr4_data_stb <= ddr4_data_out.stb and not ddr4_data_stb_d;
end generate gen_with_ddr4;
gen_without_ddr4 : if not g_WITH_DDR4 generate
ddr4_calib_done <= '0';
ddr4_wb_in <= c_DUMMY_WB_MASTER_IN;
ddr4_a_o <= (others => '0');
ddr4_ba_o <= (others => '0');
ddr4_dq_b <= (others => 'Z');
......@@ -1257,11 +1211,9 @@ begin -- architecture top
ddr4_wr_fifo_empty_o <= '0';
csr_ddr4_addr <= x"0000_0000";
ddr4_wb_out <= (adr => (others => 'X'), cyc => '0', stb => '0', sel => x"0", we => '0',
ddr4_data_out <= (adr => (others => 'X'), cyc => '0', stb => '0', sel => x"0", we => '0',
dat => (others => 'X'));
csr_ddr4_data_in <= x"0000_0000";
csr_ddr4_data_rack <= csr_ddr4_data_rd;
csr_ddr4_data_wack <= csr_ddr4_data_wr;
ddr4_data_in <= (dat => x"ffff_ffff", ack => '1', err => '0', rty => '0', stall => '0');
end generate gen_without_ddr4;
ddr4_wb_o.err <= '0';
......@@ -1336,15 +1288,15 @@ begin -- architecture top
wb1_rst_n_i => rst_gbl_n,
wb1_clk_i => clk_sys_62m5,
wb1_sel_i => ddr5_wb_out.sel,
wb1_cyc_i => ddr5_wb_out.cyc,
wb1_stb_i => ddr5_wb_out.stb,
wb1_we_i => ddr5_wb_out.we,
wb1_addr_i => ddr5_wb_out.adr,
wb1_data_i => ddr5_wb_out.dat,
wb1_data_o => ddr5_wb_in.dat,
wb1_ack_o => ddr5_wb_in.ack,
wb1_stall_o => ddr5_wb_in.stall,
wb1_sel_i => ddr5_data_out.sel,
wb1_cyc_i => ddr5_data_out.cyc,
wb1_stb_i => ddr5_data_stb,
wb1_we_i => ddr5_data_out.we,
wb1_addr_i => csr_ddr5_addr,
wb1_data_i => ddr5_data_out.dat,
wb1_data_o => ddr5_data_in.dat,
wb1_ack_o => ddr5_data_in.ack,
wb1_stall_o => ddr5_data_in.stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
......@@ -1363,8 +1315,8 @@ begin -- architecture top
ddr5_calib_done <= ddr5_status(0);
-- unused Wishbone signals
ddr5_wb_in.err <= '0';
ddr5_wb_in.rty <= '0';
ddr5_data_in.err <= '0';
ddr5_data_in.rty <= '0';
p_ddr5_addr: process (clk_sys_62m5)
begin
......@@ -1373,39 +1325,19 @@ begin -- architecture top
csr_ddr5_addr <= x"0000_0000";
elsif csr_ddr5_addr_wr = '1' then
csr_ddr5_addr <= csr_ddr5_addr_out;
elsif ddr5_wb_in.ack = '1' then
elsif ddr5_data_in.ack = '1' then
csr_ddr5_addr <= std_logic_vector(unsigned(csr_ddr5_addr) + 4);
end if;
end if;
end process;
p_ddr5_ack: process (clk_sys_62m5)
begin
if rising_edge(clk_sys_62m5) then
if rst_sys_62m5_n = '0' then
ddr5_read_ip <= '0';
ddr5_write_ip <= '0';
else
ddr5_read_ip <= csr_ddr5_data_rd or (ddr5_read_ip and not ddr5_wb_in.ack);
ddr5_write_ip <= csr_ddr5_data_wr or (ddr5_write_ip and not ddr5_wb_in.ack);
end if;
ddr5_data_stb_d <= ddr5_data_out.stb;
end if;
end process;
ddr5_wb_out <= (adr => csr_ddr5_addr,
cyc => csr_ddr5_data_rd or csr_ddr5_data_wr or ddr5_read_ip or ddr5_write_ip,
stb => csr_ddr5_data_rd or csr_ddr5_data_wr,
sel => x"f",
we => csr_ddr5_data_wr,
dat => csr_ddr5_data_out);
csr_ddr5_data_in <= ddr5_wb_in.dat;
csr_ddr5_data_rack <= ddr5_read_ip and ddr5_wb_in.ack;
csr_ddr5_data_wack <= ddr5_write_ip and ddr5_wb_in.ack;
ddr5_data_stb <= ddr5_data_out.stb and not ddr5_data_stb_d;
end generate gen_with_ddr5;
gen_without_ddr5 : if not g_WITH_DDR5 generate
ddr5_calib_done <= '0';
ddr5_wb_in <= c_DUMMY_WB_MASTER_IN;
ddr5_a_o <= (others => '0');
ddr5_ba_o <= (others => '0');
ddr5_dq_b <= (others => 'Z');
......@@ -1430,11 +1362,9 @@ begin -- architecture top
ddr5_wr_fifo_empty_o <= '0';
csr_ddr5_addr <= x"0000_0000";
ddr5_wb_out <= (adr => (others => 'X'), cyc => '0', stb => '0', sel => x"0", we => '0',
dat => (others => 'X'));
csr_ddr5_data_in <= x"0000_0000";
csr_ddr5_data_rack <= csr_ddr5_data_rd;
csr_ddr5_data_wack <= csr_ddr5_data_wr;
ddr5_data_out <= (adr => (others => 'X'), cyc => '0', stb => '0', sel => x"0", we => '0',
dat => (others => 'X'));
ddr5_data_in <= (dat => x"ffff_ffff", ack => '1', err => '0', rty => '0', stall => '0');
end generate gen_without_ddr5;
ddr5_wb_o.err <= '0';
......
hdl/syn/common/svec_base_common.ucf
View file @ aa1ec6f4
......@@ -234,15 +234,15 @@ TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMESPEC TS_ref_sync_ffs = FROM ref_clk TO "sys_sync_ffs" TIG;
TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
#TIMESPEC TS_ref_sync_ffs = FROM ref_clk TO "sys_sync_ffs" TIG;
#TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
TIMEGRP "ref_sync_reg" = "sync_reg" EXCEPT "ref_clk";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
#TIMEGRP "ref_sync_reg" = "sync_reg" EXCEPT "ref_clk";
#TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "ref_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg" 16ns DATAPATHONLY;
#TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "ref_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg" 16ns DATAPATHONLY;
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