fpga to test the vme64xcore

a67f8533 · Tristan Gingold · b9e0b1a7 · a67f8533 · a67f8533 · a67f8533
Commit a67f8533 authored Sep 28, 2017 by Tristan Gingold
8 changed files
--- a/hdl/syn/vmecore_test/Manifest.py
+++ b/hdl/syn/vmecore_test/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+syn_device = "xc6slx150t"
+syn_grade = "-3"
+syn_package = "fgg900"
+syn_top = "svec_vmecore_test_top"
+syn_project = "svec_vmecore_test_top.xise"
+syn_tool = "ise"
+
+modules = {
+    "local" : [
+        "../../top/vmecore_test",
+    ],
+}
+
+fetchto="../../ip_cores"
+
--- a/hdl/top/vmecore_test/Manifest.py
+++ b/hdl/top/vmecore_test/Manifest.py
+fetchto = "../../ip_cores"
+
+files = [
+    "svec_vmecore_test_top.vhd",
+    "svec_vmecore_test_top.ucf",
+    "vmecore_test.vhd",
+]
+
+modules = {
+    "git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git",
+              "git://ohwr.org/hdl-core-lib/vme64x-core.git" ]
+}
--- a/hdl/top/vmecore_test/vmecore_test.vhd
+++ b/hdl/top/vmecore_test/vmecore_test.vhd
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+use work.wishbone_pkg.all;
+
+entity vmecore_test is
+
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    slave_i : in  t_wishbone_slave_in;
+    slave_o : out t_wishbone_slave_out;
+
+    leds_o : out std_logic_vector(15 downto 0);
+    irq_o : out std_logic
+    );
+
+end vmecore_test;
+
+architecture rtl of vmecore_test is
+  --  Memory map:
+  --  0 - 0x1ff: sram (512B)
+  --  0x1000: leds (4B)
+  --  0x2000: counter (4B). Generate a timeout when 0 is reached.
+  signal counter : unsigned(31 downto 0);
+  signal leds : std_logic_vector(15 downto 0);
+  
+  signal last_trans : std_logic_vector (20 downto 0);
+
+  signal nbr_read : unsigned (15 downto 0);
+  signal nbr_write: unsigned (15 downto 0);
+  
+  type sram_type is array (0 to 16#1ff#) of std_logic_vector(31 downto 0);
+  signal sram: sram_type;
+begin
+  process (clk_sys_i)
+    variable idx : natural;
+  begin
+    if rising_edge(clk_sys_i) then
+      slave_o.ack <= '0';
+      slave_o.stall <= '0';
+      
+      if rst_n_i = '0' then
+        counter <= (others => '0');
+        leds <= (others => '0');
+        nbr_read <= (others => '0');
+        nbr_write <= (others => '0');
+      else
+        -- Decrementer
+        if counter /= (counter'range => '0') then
+          counter <= counter - 1;
+        end if;
+
+        if slave_i.stb = '1' then
+          if slave_i.adr (13 downto 12) = "00" then
+            last_trans (15 downto 0) <= slave_i.adr (15 downto 0);
+            last_trans (19 downto 16) <= slave_i.sel;
+            last_trans (20) <= slave_i.we;
+          end if;
+
+          if slave_i.we = '1' then
+            --  Write
+            nbr_write <= nbr_write + 1;
+            case slave_i.adr (13 downto 12) is
+              when "00" =>
+                idx := to_integer(unsigned(slave_i.adr(8 downto 0)));
+                for i in 3 downto 0 loop
+                  if slave_i.sel (i) = '1' then
+                    sram(idx)(8*i + 7 downto 8*i) <=
+                      slave_i.dat(8*i + 7 downto 8*i);
+                  end if;
+                end loop;
+              when "01" =>
+                case slave_i.adr (1 downto 0) is
+                  when "00" =>
+                    for i in 1 downto 0 loop
+                      if slave_i.sel (i) = '1' then
+                        leds(8*i + 7 downto 8*i) <=
+                          slave_i.dat(8*i + 7 downto 8*i);
+                      end if;
+                    end loop;
+                  when "01" =>
+                    null;
+                  when "10" =>
+                    nbr_read <= (others => '0');
+                  when "11" =>
+                    nbr_write <= (others => '0');
+                  when others =>
+                    null;
+                end case;
+              when "10" =>
+                for i in 3 downto 0 loop
+                  if slave_i.sel (i) = '1' then
+                    counter(8*i + 7 downto 8*i) <=
+                      unsigned(slave_i.dat(8*i + 7 downto 8*i));
+                  end if;
+                end loop;
+              when "11" =>
+                null;
+              when others =>
+                null;
+            end case;
+            slave_o.ack <= '1';
+          else
+            -- Read
+            nbr_read <= nbr_read + 1;
+            case slave_i.adr (13 downto 12) is
+              when "00" =>
+                idx := to_integer(unsigned(slave_i.adr(8 downto 0)));
+                slave_o.dat <= sram(idx);
+              when "01" =>
+                case slave_i.adr (1 downto 0) is
+                  when "00" =>
+                    slave_o.dat(31 downto 16) <= (others => '0');
+                    slave_o.dat(15 downto 0) <= leds;
+                  when "01" =>
+                    slave_o.dat <= (31 downto 21 => '0') & last_trans;
+                  when "10" =>
+                    slave_o.dat (31 downto 16) <= (others => '0');
+                    slave_o.dat (15 downto 0) <= std_logic_vector (nbr_read);
+                  when "11" =>
+                    slave_o.dat (31 downto 16) <= (others => '0');
+                    slave_o.dat (15 downto 0) <= std_logic_vector (nbr_write);
+                  when others =>
+                    null;
+                end case;
+              when "10" =>
+                slave_o.dat <= std_logic_vector(counter);
+              when "11" =>
+                slave_o.dat (31 downto 16) <= not slave_i.adr(15 downto 0);
+                slave_o.dat (15 downto 0)  <= slave_i.adr(15 downto 0);
+              when others =>
+                null;
+            end case;
+            slave_o.ack <= '1';
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  leds_o <= leds;
+  irq_o <= '1' when counter = 1 else '0';
+end rtl;
--- a/software/vmecore_test/Makefile
+++ b/software/vmecore_test/Makefile
+VMEBRIDGE=/acc/local/L867/drv/vmebus/1.0.1
+
+CC=gcc
+CFLAGS=-O -Wall
+
+all: test_vme
+
+test_vme: test_vme.o
+	$(CC) -o $@ $< $(VMEBRIDGE)/lib/libvmebus.a -lrt
+
+test_vme.o: test_vme.c
+	$(CC) -c -o $@ $< --std=c99 $(CFLAGS) -I$(VMEBRIDGE)/include/vmebus
+
+clean:
+	$(RM) -f test_vme *.o *~ *.pyc
--- a/software/vmecore_test/README
+++ b/software/vmecore_test/README
+This is the software to test the vme64xcore on SVEC.
+
+lsvme.py is a utility to display cards on the VME bus or CR/CSR of a card:
+$ ./lsvme.py
+$ ./lsvme.py -s SLOT
+(You need UAL).
+
+test_vme tests the core (many data accesses, dma, interrupts). Usage:
+$ ./test_vme -s SLOT
+
--- a/software/vmecore_test/lsvme.py
+++ b/software/vmecore_test/lsvme.py
--- a/software/vmecore_test/test_vme.c
+++ b/software/vmecore_test/test_vme.c
--- a/software/vmecore_test/test_vme.py
+++ b/software/vmecore_test/test_vme.py
+#!/usr/bin/env python
+import PyUAL
+import getopt, sys
+import lsvme
+
+nbr_err = 0
+
+def report(msg, ok):
+    global nbr_err
+    if ok:
+        s = "OK:  "
+    else:
+        s = "ERR: "
+        nbr_err += 1
+    print(s + msg)
+
+def do_test_cr(cr_csr):
+    chksum_computed = lsvme.compute_checksum(cr_csr)
+    chksum_read = cr_csr.readb(0x03)
+    report("checksum", chksum_read == chksum_computed)
+
+def do_test_mem(addr, am):
+    print("INFO: memory test using mode 0x{0:02x} {1}".format(
+            am, lsvme.AM_map[am]))
+    vme_desc = PyUAL.PyUALVME(4, am, 0x10000, addr, 0)
+    vme_acc = PyUAL.PyUAL("vme", vme_desc)
+
+    # clear
+    for i in range(0,16,4):
+        vme_acc.writel(i, 0)
+    # and check
+    for i in range(0,16,4):
+        if vme_acc.readl(i) != 0:
+            report("clear", False)
+    # Write a byte and check
+    vme_acc.writeb(3, 0xb3)
+    report("byte write at 3", vme_acc.readl(0) == 0xb3000000)
+    # Write a byte and check
+    vme_acc.writeb(0, 0x27)
+    report("byte write at 0", vme_acc.readl(0) == 0xb3000027)
+    # Write a word
+    vme_acc.writew(4, 0x3c8f)
+    report("word write at 4", vme_acc.readl(4) == 0x3c8f)
+    # Write a word
+    vme_acc.writew(6, 0x744d)
+    report("word write at 6", vme_acc.readl(4) == 0x744d3c8f)
+    # Write a long word
+    vme_acc.writel(8, 0xedcba987)
+    report("lword write at 8", vme_acc.readl(8) == 0xedcba987)
+    # Read byte
+    report("byte read at 8", vme_acc.readb(8) == 0x87)
+    report("byte read at 11", vme_acc.readb(11) == 0xed)
+    report("byte read at 9", vme_acc.readb(9) == 0xa9)
+    report("byte read at 10", vme_acc.readb(10) == 0xcb)
+
+def swap32(x):
+    return (((x << 24) & 0xFF000000) |
+            ((x <<  8) & 0x00FF0000) |
+            ((x >>  8) & 0x0000FF00) |
+            ((x >> 24) & 0x000000FF))
+
+def do_test_blt(addr, am):
+    print("INFO: BLT test using mode 0x{0:02x} {1}".format(
+            am, lsvme.AM_map[am]))
+    vme_desc = PyUAL.PyUALVME(4, am, 0x10000, addr, 0)
+    vme_acc = PyUAL.PyUAL("vme", vme_desc)
+
+    # clear
+    for i in range(0,16,4):
+        vme_acc.writel(i, 0)
+    # and check
+    for i in range(0,16,4):
+        if vme_acc.readl(i) != 0:
+            report("clear", False)
+    for i in range(0xc000, 0xc010, 4):
+        v = swap32(vme_acc.readl(i))
+        e = ((i >> 2) | ((~(i >> 2)) << 16)) & 0xffffffff
+        report("word at {0:04x} (v:{1:08x}, e:{2:08x})".format(i, v, e),
+               v == e)
+
+def main():
+    slot = None
+    try:
+        opts, args = getopt.getopt(sys.argv[1:], "s:")
+    except getopt.GetoptError as err:
+        print str(err)
+        sys.exit(2)
+    for o, a in opts:
+        if o == "-s":
+            slot = int(a)
+        else:
+            assert False, "unhandled option"
+    
+    if not slot:
+        print ("missing -s SLOT option")
+        sys.exit(1)
+
+    cr_csr_desc = PyUAL.PyUALVME(4, 0x2f, 0x80000, slot << 19, 0)
+    cr_csr = PyUAL.PyUAL("vme", cr_csr_desc)
+
+    if not lsvme.validate_cr(cr_csr):
+        print ("CR not validated")
+        sys.exit(1)
+
+    do_test_cr(cr_csr)
+
+    ader = lsvme.read_ader(cr_csr, 1)
+    adem = lsvme.read_adem(cr_csr, 1)
+    am = ader['am']
+    if am != 0x39:
+        print("unexpected AM")
+    addr = adem['addr'] & ader['addr']
+    print("INFO: addr: 0x{0:08x}, am: 0x{1:02x} {2}".format(
+            addr, am, lsvme.AM_map[am]))
+
+    am = 0x39
+    cr_csr.writeb(0x7ff63 + 1 * 0x10 + 0xc, am << 2)
+    do_test_mem(addr, am)
+
+    am = 0x3e
+    cr_csr.writeb(0x7ff63 + 1 * 0x10 + 0xc, am << 2)
+    do_test_mem(addr, am)
+
+    am = 0x3f
+    cr_csr.writeb(0x7ff63 + 1 * 0x10 + 0xc, am << 2)
+    do_test_blt(addr, am)
+
+    # Restore AM
+    am = 0x39
+    cr_csr.writeb(0x7ff63 + 1 * 0x10 + 0xc, am << 2)
+
+    # Report
+    if nbr_err == 0:
+        print("OK!!")
+        sys.exit(0)
+    else:
+        print("FAILED!!")
+        sys.exit(1)
+
+if __name__ == "__main__":
+    main()
+