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Simple VME FMC Carrier SVEC
Commits
9d0901b0
Commit
9d0901b0
authored
Sep 05, 2012
by
Matthieu Cattin
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Plain Diff
DDR memories access an address and a data register.
An address counter is automatically incremented on data r/w.
parent
3373f2e8
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3 changed files
with
157 additions
and
62 deletions
+157
-62
vme64x_ddr_tb.vhd
hdl/sim/ddr_test/testbench/vme64x_ddr_tb.vhd
+29
-28
wave_wb_buses.do
hdl/sim/ddr_test/wave_wb_buses.do
+27
-4
svec_afpga_top.vhd
hdl/top/ddr_test/svec_afpga_top.vhd
+101
-30
No files found.
hdl/sim/ddr_test/testbench/vme64x_ddr_tb.vhd
View file @
9d0901b0
...
...
@@ -663,65 +663,66 @@ begin
------------------------------------------------------------------------------
report
"START WRITE AND READ WB REG/MEMORY"
;
-- Write
RAM address 0x0
-- Write
DDR bank4 address
s_dataTransferType
<=
D32
;
s_AddressingType
<=
A32
;
s_dataToSend
<=
x"
AAAA1234
"
;
s_address
<=
x"000000000000
2
000"
;
s_dataToSend
<=
x"
00000001
"
;
s_address
<=
x"000000000000
1
000"
;
S_Write
(
v_address
=>
s_address
,
s_dataToSend
=>
s_dataToSend
,
s_dataTransferType
=>
s_dataTransferType
,
s_AddressingType
=>
s_AddressingType
,
VME64xBus_In
=>
VME64xBus_In
,
VME64xBus_Out
=>
VME64xBus_Out
);
wait
for
100
ns
;
-- Write DDR bank5 address 0x0
-- Read DDR bank4 address
s_dataTransferType
<=
D32
;
s_AddressingType
<=
A32
;
s_address
<=
x"0000000000001000"
;
s_dataToReceive
<=
x"00000001"
;
S_Read
(
v_address
=>
s_address
,
s_dataToReceive
=>
s_dataToReceive
,
s_dataTransferType
=>
s_dataTransferType
,
s_AddressingType
=>
s_AddressingType
,
VME64xBus_In
=>
VME64xBus_In
,
VME64xBus_Out
=>
VME64xBus_Out
);
wait
for
100
ns
;
-- Write DDR bank4 data
s_dataTransferType
<=
D32
;
s_AddressingType
<=
A32
;
s_dataToSend
<=
x"
55559876
"
;
s_address
<=
x"000000000000
30
00"
;
s_dataToSend
<=
x"
44444444
"
;
s_address
<=
x"000000000000
18
00"
;
S_Write
(
v_address
=>
s_address
,
s_dataToSend
=>
s_dataToSend
,
s_dataTransferType
=>
s_dataTransferType
,
s_AddressingType
=>
s_AddressingType
,
VME64xBus_In
=>
VME64xBus_In
,
VME64xBus_Out
=>
VME64xBus_Out
);
wait
for
100
ns
;
--
Read RAM address 0x0
--
Write DDR bank4 address
s_dataTransferType
<=
D32
;
s_AddressingType
<=
A32
;
s_
address
<=
x"0000000000002000
"
;
s_
dataToReceive
<=
x"AAAA1234
"
;
S_
Read
(
v_address
=>
s_address
,
s_dataToReceive
=>
s_dataToReceive
,
s_dataTransferType
=>
s_dataTransferType
,
s_AddressingType
=>
s_AddressingType
,
VME64xBus_In
=>
VME64xBus_In
,
VME64xBus_Out
=>
VME64xBus_Out
);
s_AddressingType
<=
A32
;
s_
dataToSend
<=
x"00000001
"
;
s_
address
<=
x"0000000000001000
"
;
S_
Write
(
v_address
=>
s_address
,
s_dataToSend
=>
s_dataToSend
,
s_dataTransferType
=>
s_dataTransferType
,
s_AddressingType
=>
s_AddressingType
,
VME64xBus_In
=>
VME64xBus_In
,
VME64xBus_Out
=>
VME64xBus_Out
);
wait
for
100
ns
;
-- Read DDR bank
5 address 0x0
-- Read DDR bank
4 address
s_dataTransferType
<=
D32
;
s_AddressingType
<=
A32
;
s_address
<=
x"000000000000
3
000"
;
s_dataToReceive
<=
x"
55559876
"
;
s_address
<=
x"000000000000
1
000"
;
s_dataToReceive
<=
x"
00000001
"
;
S_Read
(
v_address
=>
s_address
,
s_dataToReceive
=>
s_dataToReceive
,
s_dataTransferType
=>
s_dataTransferType
,
s_AddressingType
=>
s_AddressingType
,
VME64xBus_In
=>
VME64xBus_In
,
VME64xBus_Out
=>
VME64xBus_Out
);
wait
for
100
ns
;
-- Read DDR bank
5 address 0x0
-- Read DDR bank
4 data
s_dataTransferType
<=
D32
;
s_AddressingType
<=
A32
;
s_address
<=
x"000000000000
30
00"
;
s_dataToReceive
<=
x"
55559876
"
;
s_address
<=
x"000000000000
18
00"
;
s_dataToReceive
<=
x"
44444444
"
;
S_Read
(
v_address
=>
s_address
,
s_dataToReceive
=>
s_dataToReceive
,
s_dataTransferType
=>
s_dataTransferType
,
s_AddressingType
=>
s_AddressingType
,
VME64xBus_In
=>
VME64xBus_In
,
VME64xBus_Out
=>
VME64xBus_Out
);
wait
for
100
ns
;
-- Read DDR bank5 address 0x0
s_dataTransferType
<=
D32
;
s_AddressingType
<=
A32
;
s_address
<=
x"0000000000003000"
;
s_dataToReceive
<=
x"55559876"
;
S_Read
(
v_address
=>
s_address
,
s_dataToReceive
=>
s_dataToReceive
,
s_dataTransferType
=>
s_dataTransferType
,
s_AddressingType
=>
s_AddressingType
,
VME64xBus_In
=>
VME64xBus_In
,
VME64xBus_Out
=>
VME64xBus_Out
);
wait
for
100
ns
;
assert
false
report
"Got here!"
severity
failure
;
wait
;
...
...
hdl/sim/ddr_test/wave_wb_buses.do
View file @
9d0901b0
...
...
@@ -34,7 +34,30 @@ add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/wb_dat_i
add wave -noupdate /vme64x_ddr_tb/uut/wb_cyc
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/wb_adr
add wave -noupdate /vme64x_ddr_tb/uut/wb_ack
add wave -noupdate -divider DDR
add wave -noupdate -divider {DDR bank4}
add wave -noupdate /vme64x_ddr_tb/uut/sys_clk
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/ddr_bank4_addr_cnt
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_we_i
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_we_f_edge
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_we_d
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_stb_i
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_stb_f_edge
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_stb_d
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_cyc_r_edge
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_cyc_i
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_cyc_f_edge
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/wb_cyc_d
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_wr_en
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_wr_data
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_rd_en
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_rd_data_i
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_cmd_instr
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_cmd_en
add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_0/ddr_burst_cnt
add wave -noupdate -divider {DDR bank5}
add wave -noupdate /vme64x_ddr_tb/uut/ddr_bank5_addr_cnt
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/wb_we_i
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/wb_we_f_edge
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/wb_we_d
...
...
@@ -56,8 +79,8 @@ add wave -noupdate -radix hexadecimal /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl
add wave -noupdate /vme64x_ddr_tb/uut/cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wb_0/ddr_burst_cnt
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {17
089000
ps} 0}
configure wave -namecolwidth 5
20
WaveRestoreCursors {{Cursor 1} {17
413525
ps} 0}
configure wave -namecolwidth 5
05
configure wave -valuecolwidth 203
configure wave -justifyvalue left
configure wave -signalnamewidth 0
...
...
@@ -71,4 +94,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {1
6585011 ps} {17481412
ps}
WaveRestoreZoom {1
7207022 ps} {17844969
ps}
hdl/top/ddr_test/svec_afpga_top.vhd
View file @
9d0901b0
...
...
@@ -464,12 +464,14 @@ architecture rtl of svec_afpga_top is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant
c_WB_SLAVES_NB
:
integer
:
=
4
;
constant
c_WB_SLAVES_NB
:
integer
:
=
6
;
constant
c_WB_CSR
:
integer
:
=
0
;
constant
c_ONEWIRE
:
integer
:
=
1
;
constant
c_WB_DDR_BANK4
:
integer
:
=
2
;
constant
c_WB_DDR_BANK5
:
integer
:
=
3
;
constant
c_WB_CSR
:
integer
:
=
0
;
constant
c_ONEWIRE
:
integer
:
=
1
;
constant
c_WB_DDR_BANK4_ADDR
:
integer
:
=
2
;
constant
c_WB_DDR_BANK4_DATA
:
integer
:
=
3
;
constant
c_WB_DDR_BANK5_ADDR
:
integer
:
=
4
;
constant
c_WB_DDR_BANK5_DATA
:
integer
:
=
5
;
constant
c_ONEWIRE_NB
:
integer
:
=
1
;
...
...
@@ -558,18 +560,8 @@ architecture rtl of svec_afpga_top is
signal
fp_led_n
:
std_logic_vector
(
7
downto
0
);
-- DDR access FIFOs
signal
ddr_bank4_start_addr
:
std_logic_vector
(
31
downto
0
);
signal
ddr_bank4_addr_cnt
:
std_logic_vector
(
31
downto
0
);
signal
ddr_bank4_start_addr_wr
:
std_logic
;
signal
ddr_bank4_data_o
:
std_logic_vector
(
31
downto
0
);
signal
ddr_bank4_data_i
:
std_logic_vector
(
31
downto
0
);
signal
ddr_bank4_data_load
:
std_logic
;
signal
ddr_bank5_start_addr
:
std_logic_vector
(
31
downto
0
);
signal
ddr_bank5_addr_cnt
:
std_logic_vector
(
31
downto
0
);
signal
ddr_bank5_start_addr_wr
:
std_logic
;
signal
ddr_bank5_data_o
:
std_logic_vector
(
31
downto
0
);
signal
ddr_bank5_data_i
:
std_logic_vector
(
31
downto
0
);
signal
ddr_bank5_data_load
:
std_logic
;
signal
ddr_bank4_addr_cnt
:
unsigned
(
31
downto
0
);
signal
ddr_bank5_addr_cnt
:
unsigned
(
31
downto
0
);
-- FOR TEST
--signal ram_we : std_logic;
...
...
@@ -745,9 +737,13 @@ begin
------------------------------------------------------------------------------
-- Wishbone address decoder
-- 0x000 -> CSR
-- 0x400 -> 1-wire master
-- 0x800 -> DDR3 bank 4
-- 0xC00 -> DDR3 bank 5
-- 0x200 -> 1-wire master
-- 0x400 -> DDR3 bank 4 address register
-- 0x600 -> DDR3 bank 4 data register
-- 0x800 -> DDR3 bank 5 address register
-- 0xA00 -> DDR3 bank 5 data register
-- 0xC00 -> Unused
-- 0xE00 -> Unused
------------------------------------------------------------------------------
cmp_csr_wb_addr_decoder
:
wb_addr_decoder
generic
map
(
...
...
@@ -898,6 +894,46 @@ begin
-- q_o => wb_dat_i(c_WB_DDR_BANK4 * 32 + 31 downto c_WB_DDR_BANK4 * 32)
-- );
-- DDR bank4 FIFO access
--
-- Offset -> Description
-- 0x0 -> Start address
-- 0x1 -> Data
-- address counter
p_ddr_bank4_addr_cnt
:
process
(
sys_clk
)
begin
if
rising_edge
(
sys_clk
)
then
if
(
sys_rst_n
=
'0'
)
then
ddr_bank4_addr_cnt
<=
(
others
=>
'0'
);
elsif
(
wb_we
=
'1'
and
wb_stb
=
'1'
and
wb_cyc
(
c_WB_DDR_BANK4_ADDR
)
=
'1'
)
then
ddr_bank4_addr_cnt
<=
unsigned
(
wb_dat_o
);
elsif
(
wb_stb
=
'1'
and
wb_cyc
(
c_WB_DDR_BANK4_DATA
)
=
'1'
)
then
ddr_bank4_addr_cnt
<=
ddr_bank4_addr_cnt
+
1
;
end
if
;
end
if
;
end
process
p_ddr_bank4_addr_cnt
;
-- WB ack generation
p_ddr_bank4_addr_ack
:
process
(
sys_clk
)
begin
if
rising_edge
(
sys_clk
)
then
if
(
sys_rst_n
=
'0'
)
then
wb_ack
(
c_WB_DDR_BANK4_ADDR
)
<=
'0'
;
elsif
(
wb_cyc
(
c_WB_DDR_BANK4_ADDR
)
=
'1'
and
wb_stb
=
'1'
)
then
wb_ack
(
c_WB_DDR_BANK4_ADDR
)
<=
'1'
;
else
wb_ack
(
c_WB_DDR_BANK4_ADDR
)
<=
'0'
;
end
if
;
end
if
;
end
process
p_ddr_bank4_addr_ack
;
-- address counter read back
wb_dat_i
(
c_WB_DDR_BANK4_ADDR
*
32
+
31
downto
c_WB_DDR_BANK4_ADDR
*
32
)
<=
std_logic_vector
(
ddr_bank4_addr_cnt
);
-- Unused stall line
wb_stall
(
c_WB_DDR_BANK4_ADDR
)
<=
'0'
;
cmp_ddr_ctrl_bank4
:
ddr3_ctrl
generic
map
(
...
...
@@ -939,14 +975,14 @@ begin
wb0_clk_i
=>
sys_clk
,
wb0_sel_i
=>
wb_sel
,
wb0_cyc_i
=>
wb_cyc
(
c_WB_DDR_BANK4
),
wb0_cyc_i
=>
wb_cyc
(
c_WB_DDR_BANK4
_DATA
),
wb0_stb_i
=>
wb_stb
,
wb0_we_i
=>
wb_we
,
wb0_addr_i
=>
wb_adr
,
wb0_addr_i
=>
std_logic_vector
(
ddr_bank4_addr_cnt
)
,
wb0_data_i
=>
wb_dat_o
,
wb0_data_o
=>
wb_dat_i
(
c_WB_DDR_BANK4
*
32
+
31
downto
c_WB_DDR_BANK4
*
32
),
wb0_ack_o
=>
wb_ack
(
c_WB_DDR_BANK4
),
wb0_stall_o
=>
wb_stall
(
c_WB_DDR_BANK4
),
wb0_data_o
=>
wb_dat_i
(
c_WB_DDR_BANK4
_DATA
*
32
+
31
downto
c_WB_DDR_BANK4_DATA
*
32
),
wb0_ack_o
=>
wb_ack
(
c_WB_DDR_BANK4
_DATA
),
wb0_stall_o
=>
wb_stall
(
c_WB_DDR_BANK4
_DATA
),
p0_cmd_empty_o
=>
open
,
p0_cmd_full_o
=>
open
,
...
...
@@ -990,6 +1026,41 @@ begin
------------------------------------------------------------------------------
-- DDR3 controller bank5
------------------------------------------------------------------------------
-- address counter
p_ddr_bank5_addr_cnt
:
process
(
sys_clk
)
begin
if
rising_edge
(
sys_clk
)
then
if
(
sys_rst_n
=
'0'
)
then
ddr_bank5_addr_cnt
<=
(
others
=>
'0'
);
elsif
(
wb_we
=
'1'
and
wb_stb
=
'1'
and
wb_cyc
(
c_WB_DDR_BANK5_ADDR
)
=
'1'
)
then
ddr_bank5_addr_cnt
<=
unsigned
(
wb_dat_o
);
elsif
(
wb_stb
=
'1'
and
wb_cyc
(
c_WB_DDR_BANK5_DATA
)
=
'1'
)
then
ddr_bank5_addr_cnt
<=
ddr_bank5_addr_cnt
+
1
;
end
if
;
end
if
;
end
process
p_ddr_bank5_addr_cnt
;
-- WB ack generation
p_ddr_bank5_addr_ack
:
process
(
sys_clk
)
begin
if
rising_edge
(
sys_clk
)
then
if
(
sys_rst_n
=
'0'
)
then
wb_ack
(
c_WB_DDR_BANK5_ADDR
)
<=
'0'
;
elsif
(
wb_cyc
(
c_WB_DDR_BANK5_ADDR
)
=
'1'
and
wb_stb
=
'1'
)
then
wb_ack
(
c_WB_DDR_BANK5_ADDR
)
<=
'1'
;
else
wb_ack
(
c_WB_DDR_BANK5_ADDR
)
<=
'0'
;
end
if
;
end
if
;
end
process
p_ddr_bank5_addr_ack
;
-- address counter read back
wb_dat_i
(
c_WB_DDR_BANK5_ADDR
*
32
+
31
downto
c_WB_DDR_BANK5_ADDR
*
32
)
<=
std_logic_vector
(
ddr_bank5_addr_cnt
);
-- Unused stall line
wb_stall
(
c_WB_DDR_BANK5_ADDR
)
<=
'0'
;
cmp_ddr_ctrl_bank5
:
ddr3_ctrl
generic
map
(
g_BANK_PORT_SELECT
=>
"SVEC_BANK5_32B_32B"
,
...
...
@@ -1030,14 +1101,14 @@ begin
wb0_clk_i
=>
sys_clk
,
wb0_sel_i
=>
wb_sel
,
wb0_cyc_i
=>
wb_cyc
(
c_WB_DDR_BANK5
),
wb0_cyc_i
=>
wb_cyc
(
c_WB_DDR_BANK5
_DATA
),
wb0_stb_i
=>
wb_stb
,
wb0_we_i
=>
wb_we
,
wb0_addr_i
=>
wb_adr
,
wb0_addr_i
=>
std_logic_vector
(
ddr_bank5_addr_cnt
)
,
wb0_data_i
=>
wb_dat_o
,
wb0_data_o
=>
wb_dat_i
(
c_WB_DDR_BANK5
*
32
+
31
downto
c_WB_DDR_BANK5
*
32
),
wb0_ack_o
=>
wb_ack
(
c_WB_DDR_BANK5
),
wb0_stall_o
=>
wb_stall
(
c_WB_DDR_BANK5
),
wb0_data_o
=>
wb_dat_i
(
c_WB_DDR_BANK5
_DATA
*
32
+
31
downto
c_WB_DDR_BANK5_DATA
*
32
),
wb0_ack_o
=>
wb_ack
(
c_WB_DDR_BANK5
_DATA
),
wb0_stall_o
=>
wb_stall
(
c_WB_DDR_BANK5
_DATA
),
p0_cmd_empty_o
=>
open
,
p0_cmd_full_o
=>
open
,
...
...
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