Commit 9cd6c291 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

doc: info on the updated flasher

parent 1888b969
......@@ -61,6 +61,8 @@ This document describes the default bitstreams that come preloaded with every SV
@item @b{Golden bitstream}, residing in the Application FPGA, which allows the SVEC device driver to enumerate the mezzanines.
@end itemize
@b{Note:} The Golden bitstream is used exclusively by the SVEC device driver (@pxref{svec_driver,,3}) in conjunction with the OHWR VME64x Core (@pxref{vme64x_core,,4}). If you are using a different VME core in your FPGA design (such as the @code{VmeIntfce} which is widely used at CERN), @b{the Golden Bitstream chapter is irrelevant for your application and there is no need to install the SVEC driver.}
@chapter The Bootloader
The System FPGA bootloader allows to boot the Application FPGA from the VME bus or from the onboard Flash memory and reprogram both the System and Application bitstreams in the flash via VME (see @ref{fig:boot_modes}). The boot process goes as follows:
......@@ -183,17 +185,18 @@ Only A32/A24/D32/CSR address modifiers are supported.
@chapter Flashing the SVEC
@section Application FPGA Flash programming through VME
@section Programming Application FPGA Flash through VME
The SVEC Application FPGA can be programmed with the @code{svec-flasher} tool, located in @code{software/vme-flasher} subdirectory of the SVEC project repository. It requires a @code{.bin} format bitstream, that can be generated by Xilinx ISE by selecting ``Generate binary configuration file'' in @i{Generate Programming File} options.
The flasher requires the slot number as the first argument and the file with the bitstream as the second, just like in the example below:
@example
# ./svec-flasher.L865 12 svec-golden.bin
Programming the Application FPGA flash with bitstream svec-golden.bin.
Programming page 7651/7651.
# ./svec-flasher 5 file.bin
Bootloader version: 2
Programming the Application FPGA flash with bitstream file.bin.
Programming page 0/0.
Verification...
Programming page 0/0.
Programming page 16495/16495.
Verification...
Programming OK.
@end example
......@@ -207,6 +210,17 @@ Programming OK.
@b{Note 3:} The card must be rebooted for the new bitstream to be loaded to the Application FPGA.
@section Loading bitstream to the Application FPGA through VME
The @code{svec-flasher} tool can be also used to load a bitstream directly to the Application FPGA, without programming the Flash chip. In order to do so, pass the @code{-f} option to the flasher tool:
@example
# ./svec-flasher 5 file.bin -f
Bootloader version: 2
Booting the Application FPGA with bitstream file.bin.
Bitstream loaded, status: OK
@end example
@b{Warning:} The programming operation will not work correctly if the SVEC driver is loaded. Please unload the SVEC kernel driver before proceeding.
@section Updating the bootloader through VME
Starting from the version 2, the bootloader can update itself via VME by using the @code{svec-flasher} tool. In order to update the bootloader,
......@@ -309,6 +323,11 @@ NET "flash_miso_i" IOSTANDARD = "LVCMOS33";
@item @uref{http://www.micron.com/parts/nor-flash/serial-nor-flash/m25p128-vme6gb} - M25P series SPI Flash memory datasheet
@anchor{repo_link}
@item @uref{http://www.ohwr.org/projects/svec/repository/} - Git repository containing this document's sources and revision history (@code{doc} subdirectory) and bootloading code examples (@code{software/sveclib} subdirectory).
@anchor{svec_driver}
@item @uref{http://www.ohwr.org/projects/svec-sw/} - SVEC Linux Device Driver
@anchor{vme64x_core}
@item @uref{http://www.ohwr.org/projects/vme64x-core/} - OHWR VME64x Core Project
@end enumerate
@page
......
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