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Simple VME FMC Carrier SVEC
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Simple VME FMC Carrier SVEC
Commits
996b595a
Commit
996b595a
authored
Jan 24, 2014
by
Tomasz Wlostowski
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hdl/top/sfpga_bootloader: fixed confusing comment about 62.5 MHz system clock
parent
4d436c87
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svec_sfpga_top.vhd
hdl/top/sfpga_bootloader/svec_sfpga_top.vhd
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hdl/top/sfpga_bootloader/svec_sfpga_top.vhd
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996b595a
...
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@@ -224,7 +224,7 @@ architecture rtl of svec_sfpga_top is
signal
vme_idle
:
std_logic
;
begin
-- PLL for producing
62.5
MHz system clock (clk_sys) from a 20 MHz reference.
-- PLL for producing
83.3
MHz system clock (clk_sys) from a 20 MHz reference.
U_Sys_clk_pll
:
PLL_BASE
generic
map
(
BANDWIDTH
=>
"OPTIMIZED"
,
...
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