Commit 996b595a authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

hdl/top/sfpga_bootloader: fixed confusing comment about 62.5 MHz system clock

parent 4d436c87
......@@ -224,7 +224,7 @@ architecture rtl of svec_sfpga_top is
signal vme_idle : std_logic;
begin
-- PLL for producing 62.5 MHz system clock (clk_sys) from a 20 MHz reference.
-- PLL for producing 83.3 MHz system clock (clk_sys) from a 20 MHz reference.
U_Sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
......
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