hdl:svec_base_wr: fix typos when ddr is not configured.

This froze the board when reading a ddr data register.

hdl:svec_base_wr: fix typos when ddr is not configured.
This froze the board when reading a ddr data register.
93d943ce · Tristan Gingold · Federico Vaga · d28b0705 · 93d943ce
Commit 93d943ce authored Apr 15, 2020 by Tristan Gingold Committed by Federico Vaga Apr 15, 2020
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svec_base_wr.vhd hdl/rtl/svec_base_wr.vhd +2 -2

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--- a/hdl/rtl/svec_base_wr.vhd
+++ b/hdl/rtl/svec_base_wr.vhd
@@ -1241,7 +1241,7 @@ begin  -- architecture top
    ddr4_wb_out <= (adr => (others => 'X'), cyc => '0', stb => '0', sel => x"0", we => '0',
      dat => (others => 'X'));
    csr_ddr4_data_in <= x"0000_0000";
-    csr_ddr4_data_rack <= csr_ddr4_data_wr;
+    csr_ddr4_data_rack <= csr_ddr4_data_rd;
    csr_ddr4_data_wack <= csr_ddr4_data_wr;
  end generate gen_without_ddr4;

@@ -1414,7 +1414,7 @@ begin  -- architecture top
    ddr5_wb_out <= (adr => (others => 'X'), cyc => '0', stb => '0', sel => x"0", we => '0',
      dat => (others => 'X'));
    csr_ddr5_data_in <= x"0000_0000";
-    csr_ddr5_data_rack <= csr_ddr5_data_wr;
+    csr_ddr5_data_rack <= csr_ddr5_data_rd;
    csr_ddr5_data_wack <= csr_ddr5_data_wr;
  end generate gen_without_ddr5;