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Simple VME FMC Carrier SVEC
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Simple VME FMC Carrier SVEC
Commits
9149d19b
Commit
9149d19b
authored
Sep 06, 2021
by
Tomasz Wlostowski
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testbench: simple TB for the SFPGA+AFPGA bridged mode operation
parent
50d00dd1
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5 changed files
with
1003 additions
and
477 deletions
+1003
-477
Manifest.py
hdl/testbench/svec7_bridge/Manifest.py
+9
-1
buildinfo_pkg.vhd
hdl/testbench/svec7_bridge/buildinfo_pkg.vhd
+2
-2
main.sv
hdl/testbench/svec7_bridge/main.sv
+88
-21
run.do
hdl/testbench/svec7_bridge/run.do
+2
-2
wave.do
hdl/testbench/svec7_bridge/wave.do
+902
-451
No files found.
hdl/testbench/svec7_bridge/Manifest.py
View file @
9149d19b
...
...
@@ -8,6 +8,8 @@ syn_device = "xc7k160t"
svec_template_ucf
=
[]
board
=
"svec7"
modelsim_ini_path
=
"/home/twl/eda/modelsim-lib-2016.4"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if
locals
()
.
get
(
'fetchto'
,
None
)
is
None
:
...
...
@@ -20,7 +22,13 @@ include_dirs=[ "../../ip_cores/vme64x-core/hdl/sim/vme64x_bfm",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6"
,
"."
]
files
=
[
"main.sv"
,
"buildinfo_pkg.vhd"
]
files
=
[
"main.sv"
,
"buildinfo_pkg.vhd"
,
"../../../hdl/ip_cores/vme64x-core/hdl/rtl/platform/bridge_serdes_spartan6.vhd"
,
"../../../hdl/ip_cores/vme64x-core/hdl/rtl/platform/bridge_serdes_kintex7.vhd"
,
"ise_ip/BUFPLL.vhd"
,
"ise_ip/OSERDES2.vhd"
,
"ise_ip/ISERDES2.vhd"
];
modules
=
{
"local"
:
[
"../../rtl/svec7"
,
...
...
hdl/testbench/svec7_bridge/buildinfo_pkg.vhd
View file @
9149d19b
...
...
@@ -6,8 +6,8 @@ package buildinfo_pkg is
constant
buildinfo
:
string
:
=
"buildinfo:1"
&
LF
&
"module:main"
&
LF
&
"commit:
37d6449f7beb462d0bbb4dc73e42d4aa5371a2c0
"
&
LF
&
"commit:
54618b729a0112964f19b9bd6222f5aeb4b22865
"
&
LF
&
"syntool:modelsim"
&
LF
&
"syndate:20
19-12-09, 22:47 CE
T"
&
LF
&
"syndate:20
21-09-06, 23:34 CES
T"
&
LF
&
"synauth:Tomasz Wlostowski"
&
LF
;
end
buildinfo_pkg
;
hdl/testbench/svec7_bridge/main.sv
View file @
9149d19b
`include
"vme64x_bfm.svh"
`include
"svec_vme_buffers.svh"
module
dummy
;
mig_7series_v4_1_ddr_if_post_fifo
dupa
()
;
endmodule
import
wishbone_pkg
::*;
module
main
;
...
...
@@ -53,7 +59,6 @@ module main;
wire
afpga_clk_p
,
afpga_clk_n
;
/* -----\/----- EXCLUDED -----\/-----
svec7_sfpga_top
#(
.
g_SIMULATION
(
1'b1
)
...
...
@@ -92,7 +97,6 @@ module main;
)
;
-----/\----- EXCLUDED -----/\----- */
svec7_test_top
#(
...
...
@@ -105,14 +109,18 @@ module main;
.
clk_125m_pllref_n_i
(
~
clk_125m_pllref
)
,
.
clk_20m_vcxo_i
(
clk_local
)
,
.
clk_125m_gtx_n_i
(
clk_125m_pllref
)
,
.
clk_125m_gtx_p_i
(
~
clk_125m_pllref
)
,
.
clk_125m_gtx_115_n_i
(
clk_125m_pllref
)
,
.
clk_125m_gtx_115_p_i
(
~
clk_125m_pllref
)
,
.
clk_125m_gtx_116_n_i
(
clk_125m_pllref
)
,
.
clk_125m_gtx_116_p_i
(
~
clk_125m_pllref
)
,
.
clk_fpga2_p_i
(
clk_125m_pllref
)
,
.
clk_fpga2_n_i
(
~
clk_125m_pllref
)
,
.
clk_si57x_p_i
(
clk_125m_pllref
)
,
.
clk_si57x_n_i
(
~
clk_125m_pllref
)
,
.
sfpga_clk_p_o
(
afpga_clk_p
)
,
.
sfpga_clk_n_o
(
afpga_clk_n
)
,
...
...
@@ -155,30 +163,83 @@ module main;
.
fp_gpio3_b
(
1'b0
)
,
.
fp_gpio4_b
(
1'b0
)
)
;
// courtesy of devlib2 https://github.com/slac-epics/devlib2
`define
CSR_FN_ADER
(
N
)
('
h7ff63
+
(
N
)*'
h10
)
/* N = 0 -> 7 */
`define
MAKE_ADER
(
addr
,
mod
)
(
((
addr
)&'
hffffff00
)
|
(
((
mod
)&'
h3f
)<<
2
)
)
`define
VME_AM_A24_SINGLE
'
h39
`define
VME_AM_A32_MBLT
'
h8
task
automatic
vme_csr_write32
(
ref
CBusAccessor_VME64x
acc
,
input
uint32_t
addr
,
input
uint32_t
data
)
;
acc
.
write
(
addr
,
(
data
>>
24
)
&
'hff
,
A32
|
CR_CSR
|
D08Byte3
)
;
acc
.
write
(
addr
+
4
,
(
data
>>
16
)
&
'hff
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
addr
+
8
,
(
data
>>
8
)
&
'hff
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
addr
+
12
,
data
&
'hff
,
CR_CSR
|
A32
|
D08Byte3
)
;
endtask
// vme_csr_write32
task
automatic
init_vme64x_core
(
ref
CBusAccessor_VME64x
acc
)
;
uint64_t
rv
;
/* map func0 to 0x80000000, A32 */
/* map func0 to 0x80000000, A32 MBLT */
vme_csr_write32
(
acc
,
`CSR_FN_ADER
(
0
)
,
`MAKE_ADER
(
'h80000000
,
`VME_AM_A32_MBLT
)
)
;
/* map func1 to 0x800000, A24 single access */
vme_csr_write32
(
acc
,
`CSR_FN_ADER
(
1
)
,
`MAKE_ADER
(
'h800000
,
`VME_AM_A24_SINGLE
)
)
;
acc
.
write
(
'h7ff63
,
'h80
,
A32
|
CR_CSR
|
D08Byte3
)
;
acc
.
write
(
'h7ff67
,
0
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7ff6b
,
0
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7ff6f
,
32
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7ff33
,
1
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7fffb
,
'h10
,
CR_CSR
|
A32
|
D08Byte3
)
;
/* enable module (BIT_SET = 0x10) */
acc
.
read
(
'h7ff63
,
rv
,
CR_CSR
|
A32
|
D08Byte3
)
;
//
acc.read( 'h7ff63, rv, CR_CSR|A32|D08Byte3);
$
display
(
"Rv %x"
,
rv
)
;
//
$display("Rv %x", rv );
acc
.
set_default_modifiers
(
A
32
|
D32
|
SINGLE
)
;
acc
.
set_default_modifiers
(
A
24
|
D32
|
SINGLE
)
;
endtask
// init_vme64x_core
`define
SXLDR_REG_CSR
'
h00000000
`define
SXLDR_REG_BTRIGR
'
h00000004
`define
SXLDR_REG_FAR
'
h00000008
`define
SXLDR_REG_IDR
'
h0000000c
task
automatic
check_svec_bootloader
(
ref
CBusAccessor_VME64x
acc
)
;
int
i
;
uint64_t
rv
;
uint32_t
boot_seq
[
8
]
=
'
{
'hde
,
'had
,
'hbe
,
'hef
,
'hca
,
'hfe
,
'hba
,
'hbe
};
/* magic sequence: unlock bootloader mode, disable application FPGA */
for
(
i
=
0
;
i
<
8
;
i
++
)
acc
.
write
(
'h70000
+
`SXLDR_REG_BTRIGR
,
boot_seq
[
i
]
,
CR_CSR
|
A32
|
D32
)
;
#
10u
s
;
acc
.
read
(
'h70000
+
`SXLDR_REG_IDR
,
rv
,
CR_CSR
|
A32
|
D32
)
;
$
display
(
"Boot IDR = 0x%x"
,
rv
)
;
acc
.
write
(
'h70000
+
`SXLDR_REG_CSR
,
(
1
<<
6
)
,
CR_CSR
|
A32
|
D32
)
;
// exit boot mode
#
1u
s
;
// if (csr_readl(SXLDR_REG_IDR) != 0x53564543) { /* "SVEC" in hex */
endtask
// check_vme_bootloader
initial
begin
uint64_t
d
;
...
...
@@ -192,23 +253,28 @@ module main;
automatic
CBusAccessor_VME64x
acc
=
new
(
VME
.
tb
)
;
// automatic CWishboneAccessor ddr4_acc = xwb_ddr4.get_accessor();
#
5
u
s
;
#
60
u
s
;
init_vme64x_core
(
acc
)
;
check_svec_bootloader
(
acc
)
;
// Display meta data
d
=
'hdeadbeef
;
acc
.
write
(
'h8
000
0000
,
d
,
A24
|
SINGLE
|
D32
)
;
acc
.
write
(
'h8
2
0000
,
d
,
A24
|
SINGLE
|
D32
)
;
d
=
'hcafebabe
;
acc
.
write
(
'h8
000
0004
,
d
,
A24
|
SINGLE
|
D32
)
;
acc
.
write
(
'h8
2
0004
,
d
,
A24
|
SINGLE
|
D32
)
;
acc
.
read
(
'h8
000
0000
,
d
,
A24
|
SINGLE
|
D32
)
;
acc
.
read
(
'h8
2
0000
,
d
,
A24
|
SINGLE
|
D32
)
;
$
display
(
"Rdbk[0] = %x"
,
d
)
;
acc
.
read
(
'h8
000
0004
,
d
,
A24
|
SINGLE
|
D32
)
;
acc
.
read
(
'h8
2
0004
,
d
,
A24
|
SINGLE
|
D32
)
;
$
display
(
"Rdbk[4] = %x"
,
d
)
;
//$display("ddr status: %x", d);
addr
[
0
]
=
'h800
01
000
;
addr
[
0
]
=
'h800
20
000
;
t_start
=
real
'
($
time
)
/
real
'
(
1u
s
)
;
...
...
@@ -217,6 +283,7 @@ module main;
$
display
(
"mblt : %d bytes / %.0f us = approx %.0f bytes / second"
,
data
.
size
()
*
4
,
t_end
-
t_start
,
real
'
(
data
.
size
())
*
4
*
1e6
/
(
t_end
-
t_start
))
;
$
stop
;
end
...
...
hdl/testbench/svec7_bridge/run.do
View file @
9149d19b
vsim -t 1ps -quiet -L unisims_ver -L secureip work.main work.glbl
vsim -t 1ps -quiet -L unisims_ver -L secureip
-voptargs=+acc
work.main work.glbl
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
...
...
@@ -7,6 +7,6 @@ radix -hexadecimal
do wave.do
run 10us
run 10
0
us
wave zoomfull
hdl/testbench/svec7_bridge/wave.do
View file @
9149d19b
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