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Simple VME FMC Carrier SVEC
Commit 7c4136db authored by Tristan Gingold's avatar Tristan Gingold
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Add initial version of svec template.

parent 481562e0
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hdl/rtl/Manifest.py 0 → 100644
View file @ 7c4136db
# User should define the variable svec_template_ucf
files = ["svec_template_regs.vhd",
"svec_template_wr.vhd", "svec_template_common.ucf" ]
if "ddr4" in svec_template_ucf:
files.append("svec_template_ddr4.ucf")
if "ddr5" in svec_template_ucf:
files.append("svec_template_ddr5.ucf")
hdl/rtl/svec_template_common.ucf 0 → 100644
View file @ 7c4136db
This diff is collapsed.
hdl/rtl/svec_template_ddr4.ucf 0 → 100644
View file @ 7c4136db
# DDR0 (bank 4)
NET "ddr4_rzq_b" LOC = L7;
NET "ddr4_we_n_o" LOC = F4;
NET "ddr4_udqs_p_b" LOC = K2;
NET "ddr4_udqs_n_b" LOC = K1;
NET "ddr4_udm_o" LOC = K4;
NET "ddr4_reset_n_o" LOC = G5;
NET "ddr4_ras_n_o" LOC = C1;
NET "ddr4_odt_o" LOC = E4;
NET "ddr4_ldqs_p_b" LOC = J5;
NET "ddr4_ldqs_n_b" LOC = J4;
NET "ddr4_ldm_o" LOC = K3;
NET "ddr4_cke_o" LOC = C4;
NET "ddr4_ck_p_o" LOC = E3;
NET "ddr4_ck_n_o" LOC = E1;
NET "ddr4_cas_n_o" LOC = B1;
NET "ddr4_dq_b[15]" LOC = M1;
NET "ddr4_dq_b[14]" LOC = M2;
NET "ddr4_dq_b[13]" LOC = L1;
NET "ddr4_dq_b[12]" LOC = L3;
NET "ddr4_dq_b[11]" LOC = L4;
NET "ddr4_dq_b[10]" LOC = L5;
NET "ddr4_dq_b[9]" LOC = M3;
NET "ddr4_dq_b[8]" LOC = M4;
NET "ddr4_dq_b[7]" LOC = H1;
NET "ddr4_dq_b[6]" LOC = H2;
NET "ddr4_dq_b[5]" LOC = G1;
NET "ddr4_dq_b[4]" LOC = G3;
NET "ddr4_dq_b[3]" LOC = J1;
NET "ddr4_dq_b[2]" LOC = J3;
NET "ddr4_dq_b[1]" LOC = H3;
NET "ddr4_dq_b[0]" LOC = H4;
NET "ddr4_ba_o[2]" LOC = F3;
NET "ddr4_ba_o[1]" LOC = D1;
NET "ddr4_ba_o[0]" LOC = D2;
NET "ddr4_a_o[13]" LOC = B5;
NET "ddr4_a_o[12]" LOC = A4;
NET "ddr4_a_o[11]" LOC = G4;
NET "ddr4_a_o[10]" LOC = D5;
NET "ddr4_a_o[9]" LOC = A2;
NET "ddr4_a_o[8]" LOC = B2;
NET "ddr4_a_o[7]" LOC = B3;
NET "ddr4_a_o[6]" LOC = F1;
NET "ddr4_a_o[5]" LOC = F2;
NET "ddr4_a_o[4]" LOC = C5;
NET "ddr4_a_o[3]" LOC = E5;
NET "ddr4_a_o[2]" LOC = A3;
NET "ddr4_a_o[1]" LOC = D3;
NET "ddr4_a_o[0]" LOC = D4;
# DDR IO standards and terminations
NET "ddr4_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr4_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr4_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr4_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr4_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr4_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr4_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr4_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr4_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr4_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr4_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr4_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr4_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr4_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr4_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr4_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr4_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr4_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr4_dq_b[*]" IN_TERM = NONE;
NET "ddr4_ldqs_p_b" IN_TERM = NONE;
NET "ddr4_ldqs_n_b" IN_TERM = NONE;
NET "ddr4_udqs_p_b" IN_TERM = NONE;
NET "ddr4_udqs_n_b" IN_TERM = NONE;
hdl/rtl/svec_template_ddr5.ucf 0 → 100644
View file @ 7c4136db
# DDR1 (bank 5)
NET "ddr5_rzq_b" LOC = G25;
NET "ddr5_we_n_o" LOC = E26;
NET "ddr5_udqs_p_b" LOC = K28;
NET "ddr5_udqs_n_b" LOC = K30;
NET "ddr5_udm_o" LOC = J27;
NET "ddr5_reset_n_o" LOC = C26;
NET "ddr5_ras_n_o" LOC = K26;
NET "ddr5_odt_o" LOC = E30;
NET "ddr5_ldqs_p_b" LOC = J29;
NET "ddr5_ldqs_n_b" LOC = J30;
NET "ddr5_ldm_o" LOC = J28;
NET "ddr5_cke_o" LOC = B29;
NET "ddr5_ck_p_o" LOC = E27;
NET "ddr5_ck_n_o" LOC = E28;
NET "ddr5_cas_n_o" LOC = K27;
NET "ddr5_dq_b[15]" LOC = M30;
NET "ddr5_dq_b[14]" LOC = M28;
NET "ddr5_dq_b[13]" LOC = M27;
NET "ddr5_dq_b[12]" LOC = M26;
NET "ddr5_dq_b[11]" LOC = L30;
NET "ddr5_dq_b[10]" LOC = L29;
NET "ddr5_dq_b[9]" LOC = L28;
NET "ddr5_dq_b[8]" LOC = L27;
NET "ddr5_dq_b[7]" LOC = F30;
NET "ddr5_dq_b[6]" LOC = F28;
NET "ddr5_dq_b[5]" LOC = G28;
NET "ddr5_dq_b[4]" LOC = G27;
NET "ddr5_dq_b[3]" LOC = G30;
NET "ddr5_dq_b[2]" LOC = G29;
NET "ddr5_dq_b[1]" LOC = H30;
NET "ddr5_dq_b[0]" LOC = H28;
NET "ddr5_ba_o[2]" LOC = D26;
NET "ddr5_ba_o[1]" LOC = C27;
NET "ddr5_ba_o[0]" LOC = D27;
NET "ddr5_a_o[13]" LOC = A28;
NET "ddr5_a_o[12]" LOC = B30;
NET "ddr5_a_o[11]" LOC = A26;
NET "ddr5_a_o[10]" LOC = F26;
NET "ddr5_a_o[9]" LOC = A27;
NET "ddr5_a_o[8]" LOC = B27;
NET "ddr5_a_o[7]" LOC = C29;
NET "ddr5_a_o[6]" LOC = H27;
NET "ddr5_a_o[5]" LOC = H26;
NET "ddr5_a_o[4]" LOC = F27;
NET "ddr5_a_o[3]" LOC = E29;
NET "ddr5_a_o[2]" LOC = C30;
NET "ddr5_a_o[1]" LOC = D30;
NET "ddr5_a_o[0]" LOC = D28;
# DDR IO standards and terminations
NET "ddr5_udqs_p_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_udqs_n_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ldqs_p_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ldqs_n_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ck_p_o[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ck_n_o[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_rzq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_we_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_udm_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_reset_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_ras_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_odt_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_ldm_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_cke_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_cas_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_dq_b[*]" IN_TERM = NONE;
NET "ddr5_ldqs_p_b[*]" IN_TERM = NONE;
NET "ddr5_ldqs_n_b[*]" IN_TERM = NONE;
NET "ddr5_udqs_p_b[*]" IN_TERM = NONE;
NET "ddr5_udqs_n_b[*]" IN_TERM = NONE;
hdl/rtl/svec_template_regs.cheby 0 → 100644
View file @ 7c4136db
memory-map:
name: svec_template_regs
bus: wb-32-be
size: 0x2000
children:
- submap:
name: metadata
description: a ROM containing the carrier metadata
size: 0x40
interface: sram
- block:
name: csr
description: carrier and fmc status and control
address: 0x40
children:
- reg:
name: app_offset
description: offset to the application metadata
access: ro
width: 32
- reg:
name: resets
description: global and application resets
access: rw
width: 32
children:
- field:
name: global
range: 0
- field:
name: appl
range: 1
- reg:
name: fmc_presence
description: presence lines for the fmcs
access: ro
width: 32
- reg:
name: unused0
description: unused (status of gennum)
access: ro
width: 32
preset: 0
x-hdl:
type: const
- reg:
name: ddr_status
description: status of the ddr controllers
access: ro
width: 32
children:
- field:
description: Set when ddr4 calibration is done.
name: ddr4_calib_done
range: 0
- field:
description: Set when ddr5 calibration is done.
name: ddr5_calib_done
range: 1
- reg:
name: pcb_rev
description: pcb revision
access: ro
width: 32
children:
- field:
name: rev
range: 4-0
- submap:
name: therm_id
description: Thermometer and unique id
address: 0x70
size: 0x10
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: fmc_i2c
description: i2c controllers to the fmcs
address: 0x80
size: 0x20
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: flash_spi
description: spi controller to the flash
address: 0xa0
size: 0x20
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: vic
description: vector interrupt controller
address: 0x100
size: 0x100
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: buildinfo
description: a ROM containing build information
size: 0x100
interface: sram
- submap:
name: wrc_regs
address: 0x1000
description: white-rabbit core registers
size: 0x1000
interface: wb-32-be
x-hdl:
busgroup: True
hdl/rtl/svec_template_regs.vhd 0 → 100644
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hdl/rtl/svec_template_wr.ucf 0 → 100644
View file @ 7c4136db
#===============================================================================
# IO Constraints
#===============================================================================
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "clk_125m_gtp_p_i" LOC = B19;
NET "clk_125m_gtp_n_i" LOC = A19;
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# SFP slot
#----------------------------------------
NET "sfp_txp_o" LOC = B23;
NET "sfp_txn_o" LOC = A23;
NET "sfp_rxp_i" LOC = D22;
NET "sfp_rxn_i" LOC = C22;
NET "sfp_los_i" LOC = W25;
NET "sfp_mod_def0_i" LOC = Y26;
NET "sfp_mod_def1_b" LOC = Y27;
NET "sfp_mod_def2_b" LOC = AA24;
NET "sfp_rate_select_o" LOC = W24;
NET "sfp_tx_disable_o" LOC = AA25;
NET "sfp_tx_fault_i" LOC = AA27;
NET "sfp_los_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS33";
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# DAC interfaces (for VCXO)
#----------------------------------------
NET "pll20dac_din_o" LOC = U28;
NET "pll20dac_sclk_o" LOC = AA28;
NET "pll20dac_sync_n_o" LOC = N28;
NET "pll25dac_din_o" LOC = P25;
NET "pll25dac_sclk_o" LOC = N27;
NET "pll25dac_sync_n_o" LOC = P26;
NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_txd_o" LOC = U27;
NET "uart_rxd_i" LOC = U25;
NET "uart_txd_o" IOSTANDARD = "LVCMOS33";
NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
#===============================================================================
# Timing Constraints
#===============================================================================
#----------------------------------------
# Clocks
#----------------------------------------
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp;
TIMESPEC TS_clk_125m_gtp = PERIOD "clk_125m_gtp" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo";
TIMESPEC TS_clk_20m_vcxo = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%;
NET "gen_wr.cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
#----------------------------------------
# WR DMTD tweaks
#----------------------------------------
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# Declaration of domains
NET "clk_sys_62m5" TNM_NET = sys_clk_62_5;
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "clk_ddr_333m" TNM_NET = ddr_clk;
NET "cmp_xwrc_board_svec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
NET "gen_fmc_mezzanine[0].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs0_clk;
NET "gen_fmc_mezzanine[1].*/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs1_clk;
NET "gen_with_ddr[?].cmp_ddr_ctrl_bank/*/memc4_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "gen_with_ddr[?].cmp_ddr_ctrl_bank/*/memc4_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
TIMEGRP "dmtd_sync_ffs" = "sync_ffs" EXCEPT "clk_dmtd";
TIMEGRP "ddr_sync_ffs" = "sync_ffs" EXCEPT "ddr_clk";
TIMEGRP "phy_sync_ffs" = "sync_ffs" EXCEPT "phy_clk";
TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd TO "dmtd_sync_ffs" TIG;
#TIMESPEC TS_ddr_sync_ffs = FROM ddr_clk TO "ddr_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs = FROM phy_clk TO "phy_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
#TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
#TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";
TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_clk";
TIMESPEC TS_sys_62m5_sync_reg = FROM sys_clk_62_5 TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_sys_125m_sync_reg = FROM clk_125m_pllref TO "sys_sync_reg" 8ns DATAPATHONLY;
#TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
hdl/rtl/svec_template_wr.vhd 0 → 100644
View file @ 7c4136db
This diff is collapsed.
hdl/syn/golden/Manifest.py
View file @ 7c4136db
target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_top"
syn_project = "svec_top.xise"
syn_project = "svec_golden.xise"
syn_tool = "ise"
syn_top = "svec_golden"
board = "svec"
ctrls = ["bank4_64b_32b"]
svec_template_ucf = ['ddr4']
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/golden",
],
"local" : [
"../../top/golden",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
fetchto="../../ip_cores"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
hdl/syn/golden/syn_extra_steps.tcl 0 → 100644
View file @ 7c4136db
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/top/golden/Manifest.py
View file @ 7c4136db
files = [ "svec_top.vhd", "svec_top.ucf", "synthesis_descriptor.vhd" ]
fetchto = "../../ip_cores"
modules = {
"local": [ "../../platform", "../../rtl/golden" ],
"git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git" ]
}
files = ["svec_golden.vhd" ]
modules = {'local': ["../../rtl"]}
hdl/top/golden/svec_golden.vhd 0 → 100644
View file @ 7c4136db
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