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Simple VME FMC Carrier SVEC
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Simple VME FMC Carrier SVEC
Commits
7381dcab
Commit
7381dcab
authored
Jul 19, 2019
by
Tristan Gingold
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Update svec template.
parent
7c4136db
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4 changed files
with
30 additions
and
861 deletions
+30
-861
svec_template_wr.vhd
hdl/rtl/svec_template_wr.vhd
+30
-79
svec_top.ucf
hdl/top/golden/svec_top.ucf
+0
-263
svec_top.vhd
hdl/top/golden/svec_top.vhd
+0
-462
synthesis_descriptor.vhd
hdl/top/golden/synthesis_descriptor.vhd
+0
-57
No files found.
hdl/rtl/svec_template_wr.vhd
View file @
7381dcab
...
...
@@ -486,67 +486,22 @@ begin -- architecture top
vme_data_dir_o
<=
vme_data_dir_int
;
-- Mini-crossbar from gennum to carrier and application bus.
carrier_app_xb
:
process
(
clk_sys_62m5
)
is
type
t_ca_state
is
(
S_IDLE
,
S_APP
,
S_CARRIER
);
variable
ca_state
:
t_ca_state
;
variable
can_stall
:
std_logic
;
constant
c_IDLE_WB_MASTER_IN
:
t_wishbone_master_in
:
=
(
ack
=>
'0'
,
err
=>
'0'
,
rty
=>
'0'
,
stall
=>
'0'
,
dat
=>
c_DUMMY_WB_DATA
);
begin
if
rising_edge
(
clk_sys_62m5
)
then
if
rst_sys_62m5_n
=
'0'
then
ca_state
:
=
S_IDLE
;
vme_wb_in
<=
c_IDLE_WB_MASTER_IN
;
app_wb_o
<=
c_DUMMY_WB_MASTER_OUT
;
carrier_wb_in
<=
c_DUMMY_WB_MASTER_OUT
;
else
case
ca_state
is
when
S_IDLE
=>
vme_wb_in
<=
c_IDLE_WB_MASTER_IN
;
app_wb_o
<=
c_DUMMY_WB_MASTER_OUT
;
carrier_wb_in
<=
c_DUMMY_WB_MASTER_OUT
;
if
vme_wb_out
.
cyc
=
'1'
and
vme_wb_out
.
stb
=
'1'
then
-- New transaction.
-- Stall so that there is no new requests from the master.
vme_wb_in
.
stall
<=
'1'
;
can_stall
:
=
'1'
;
if
vme_wb_out
.
adr
(
31
downto
13
)
=
(
31
downto
13
=>
'0'
)
then
ca_state
:
=
S_CARRIER
;
-- Pass to carrier
carrier_wb_in
<=
vme_wb_out
;
else
ca_state
:
=
S_APP
;
app_wb_o
<=
vme_wb_out
;
end
if
;
end
if
;
when
S_CARRIER
=>
-- Pass from carrier.
-- Maintain stb as long as the carrier stalls.
carrier_wb_in
.
stb
<=
carrier_wb_out
.
stall
and
can_stall
;
can_stall
:
=
can_stall
and
carrier_wb_out
.
stall
;
vme_wb_in
<=
carrier_wb_out
;
vme_wb_in
.
stall
<=
'1'
;
if
carrier_wb_out
.
ack
=
'1'
then
ca_state
:
=
S_IDLE
;
end
if
;
when
S_APP
=>
-- Pass from application
app_wb_o
.
stb
<=
app_wb_i
.
stall
and
can_stall
;
can_stall
:
=
can_stall
and
app_wb_i
.
stall
;
vme_wb_in
<=
app_wb_i
;
vme_wb_in
.
stall
<=
'1'
;
if
app_wb_i
.
ack
=
'1'
or
app_wb_i
.
err
=
'1'
then
ca_state
:
=
S_IDLE
;
end
if
;
end
case
;
end
if
;
end
if
;
end
process
carrier_app_xb
;
inst_split
:
entity
work
.
xwb_split
generic
map
(
g_mask
=>
x"ffff_e000"
)
port
map
(
clk_sys_i
=>
clk_sys_62m5
,
rst_n_i
=>
rst_sys_62m5_n
,
slave_i
=>
vme_wb_out
,
slave_o
=>
vme_wb_in
,
master_i
(
0
)
=>
carrier_wb_out
,
master_i
(
1
)
=>
app_wb_i
,
master_o
(
0
)
=>
carrier_wb_in
,
master_o
(
1
)
=>
app_wb_o
);
i
_devs
:
entity
work
.
svec_template_regs
i
nst_carrier
:
entity
work
.
svec_template_regs
port
map
(
rst_n_i
=>
rst_sys_62m5_n
,
clk_i
=>
clk_sys_62m5
,
...
...
@@ -638,17 +593,17 @@ begin -- architecture top
if
g_WITH_ONEWIRE
and
not
g_WITH_WR
then
metadata_data
(
1
)
<=
'1'
;
end
if
;
if
g_WITH_SPI
and
not
g_WITH_WR
then
if
g_WITH_SPI
then
metadata_data
(
2
)
<=
'1'
;
end
if
;
if
g_WITH_WR
then
metadata_data
(
3
)
<=
'1'
;
end
if
;
-- Buildinfo
metadata_data
(
4
)
<=
'1'
;
if
g_WITH_DDR4
then
metadata_data
(
4
)
<=
'1'
;
metadata_data
(
5
)
<=
'1'
;
end
if
;
-- Buildinfo
metadata_data
(
5
)
<=
'1'
;
if
g_WITH_DDR5
then
metadata_data
(
6
)
<=
'1'
;
end
if
;
...
...
@@ -698,7 +653,7 @@ begin -- architecture top
rst_ref_125m_n_o
<=
rst_ref_125m_n
and
rst_csr_app_sync_n
;
clk_ref_125m_o
<=
clk_ref_125m
;
i_i2c
:
entity
work
.
xwb_i2c_master
i
nst
_i2c
:
entity
work
.
xwb_i2c_master
generic
map
(
g_interface_mode
=>
CLASSIC
,
g_address_granularity
=>
BYTE
,
...
...
@@ -833,11 +788,11 @@ begin -- architecture top
-- Uart
uart_rxd_i
=>
uart_rxd_i
,
uart_txd_o
=>
uart_txd_o
,
-- SPI Flash
spi_sclk_o
=>
spi_sclk_o
,
spi_ncs_o
=>
spi_ncs_o
,
spi_mosi_o
=>
spi_mosi_o
,
spi_miso_i
=>
spi_miso_i
,
-- SPI Flash
(not used)
spi_sclk_o
=>
open
,
spi_ncs_o
=>
open
,
spi_mosi_o
=>
open
,
spi_miso_i
=>
'0'
,
wb_slave_o
=>
wrc_in
,
wb_slave_i
=>
wrc_out_sh
,
...
...
@@ -895,13 +850,8 @@ begin -- architecture top
-- WR means neither onewire nor spi.
assert
not
g_WITH_ONEWIRE
report
"WR is not yet compatible with ONEWIRE"
severity
failure
;
assert
not
g_WITH_SPI
report
"WR is not yet compatible with SPI"
severity
failure
;
therm_id_in
<=
(
ack
=>
'1'
,
err
=>
'0'
,
rty
=>
'0'
,
stall
=>
'0'
,
dat
=>
(
others
=>
'0'
));
flash_spi_in
<=
(
ack
=>
'1'
,
err
=>
'0'
,
rty
=>
'0'
,
stall
=>
'0'
,
dat
=>
(
others
=>
'0'
));
irqs
(
1
)
<=
'0'
;
end
generate
;
gen_no_wr
:
if
not
g_WITH_WR
generate
...
...
@@ -1015,7 +965,7 @@ begin -- architecture top
onewire_b
<=
'Z'
;
end
generate
;
gen_spi
:
if
g_WITH_SPI
and
not
g_WITH_WR
generate
gen_spi
:
if
g_WITH_SPI
generate
i_spi
:
entity
work
.
xwb_spi
generic
map
(
g_interface_mode
=>
CLASSIC
,
...
...
@@ -1038,8 +988,9 @@ begin -- architecture top
);
end
generate
;
gen_no_spi
:
if
not
g_WITH_SPI
and
not
g_WITH_WR
generate
gen_no_spi
:
if
not
g_WITH_SPI
generate
flash_spi_in
<=
(
ack
=>
'1'
,
err
=>
'0'
,
rty
=>
'0'
,
stall
=>
'0'
,
dat
=>
x"00000000"
);
irqs
(
1
)
<=
'0'
;
end
generate
;
-- DDR3 controller
...
...
@@ -1140,7 +1091,7 @@ begin -- architecture top
ddr4_wb_in
.
rty
<=
'0'
;
end
generate
gen_with_ddr4
;
gen_without_ddr
:
if
not
g_WITH_DDR4
generate
gen_without_ddr
4
:
if
not
g_WITH_DDR4
generate
ddr4_calib_done
<=
'0'
;
ddr4_wb_in
<=
c_DUMMY_WB_MASTER_IN
;
ddr4_a_o
<=
(
others
=>
'0'
);
...
...
@@ -1165,7 +1116,7 @@ begin -- architecture top
ddr4_wb_o
.
ack
<=
'1'
;
ddr4_wb_o
.
stall
<=
'0'
;
ddr4_wr_fifo_empty_o
<=
'0'
;
end
generate
gen_without_ddr
;
end
generate
gen_without_ddr
4
;
ddr4_wb_o
.
err
<=
'0'
;
ddr4_wb_o
.
rty
<=
'0'
;
...
...
hdl/top/golden/svec_top.ucf
deleted
100644 → 0
View file @
7c4136db
#===============================================================================
# IO Location Constraints
#===============================================================================
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" LOC = R1;
NET "vme_rst_n_i" LOC = P4;
#NET "vme_sysclk_i" LOC = P3;
NET "vme_retry_oe_o" LOC = R4;
NET "vme_retry_n_o" LOC = AB2;
NET "vme_lword_n_b" LOC = M7;
NET "vme_iackout_n_o" LOC = N3;
NET "vme_iackin_n_i" LOC = P7;
NET "vme_iack_n_i" LOC = N1;
NET "vme_ga_i[5]" LOC = M6;
NET "vme_dtack_oe_o" LOC = T1;
NET "vme_dtack_n_o" LOC = R5;
NET "vme_ds_n_i[1]" LOC = Y7;
NET "vme_ds_n_i[0]" LOC = Y6;
NET "vme_data_oe_n_o" LOC = P1;
NET "vme_data_dir_o" LOC = P2;
NET "vme_berr_o" LOC = R3;
NET "vme_as_n_i" LOC = P6;
NET "vme_addr_oe_n_o" LOC = N4;
NET "vme_addr_dir_o" LOC = N5;
NET "vme_irq_n_o[6]" LOC = R7;
NET "vme_irq_n_o[5]" LOC = AH2;
NET "vme_irq_n_o[4]" LOC = AF2;
NET "vme_irq_n_o[3]" LOC = N9;
NET "vme_irq_n_o[2]" LOC = N10;
NET "vme_irq_n_o[1]" LOC = AH4;
NET "vme_irq_n_o[0]" LOC = AG4;
NET "vme_ga_i[4]" LOC = V9;
NET "vme_ga_i[3]" LOC = V10;
NET "vme_ga_i[2]" LOC = AJ1;
NET "vme_ga_i[1]" LOC = AH1;
NET "vme_ga_i[0]" LOC = V7;
NET "vme_data_b[31]" LOC = AK3;
NET "vme_data_b[30]" LOC = AH3;
NET "vme_data_b[29]" LOC = T8;
NET "vme_data_b[28]" LOC = T9;
NET "vme_data_b[27]" LOC = AK4;
NET "vme_data_b[26]" LOC = AJ4;
NET "vme_data_b[25]" LOC = W6;
NET "vme_data_b[24]" LOC = W7;
NET "vme_data_b[23]" LOC = AB6;
NET "vme_data_b[22]" LOC = AB7;
NET "vme_data_b[21]" LOC = W9;
NET "vme_data_b[20]" LOC = W10;
NET "vme_data_b[19]" LOC = AK5;
NET "vme_data_b[18]" LOC = AH5;
NET "vme_data_b[17]" LOC = AD6;
NET "vme_data_b[16]" LOC = AC6;
NET "vme_data_b[15]" LOC = AA6;
NET "vme_data_b[14]" LOC = AA7;
NET "vme_data_b[13]" LOC = T6;
NET "vme_data_b[12]" LOC = T7;
NET "vme_data_b[11]" LOC = AG5;
NET "vme_data_b[10]" LOC = AE5;
NET "vme_data_b[9]" LOC = Y11;
NET "vme_data_b[8]" LOC = W11;
NET "vme_data_b[7]" LOC = AF6;
NET "vme_data_b[6]" LOC = AE6;
NET "vme_data_b[5]" LOC = Y8;
NET "vme_data_b[4]" LOC = Y9;
NET "vme_data_b[3]" LOC = AE7;
NET "vme_data_b[2]" LOC = AD7;
NET "vme_data_b[1]" LOC = AA9;
NET "vme_data_b[0]" LOC = AA10;
NET "vme_am_i[5]" LOC = V8;
NET "vme_am_i[4]" LOC = AG3;
NET "vme_am_i[3]" LOC = AF3;
NET "vme_am_i[2]" LOC = AF4;
NET "vme_am_i[1]" LOC = AE4;
NET "vme_am_i[0]" LOC = AK2;
NET "vme_addr_b[31]" LOC = T2;
NET "vme_addr_b[30]" LOC = T3;
NET "vme_addr_b[29]" LOC = T4;
NET "vme_addr_b[28]" LOC = U1;
NET "vme_addr_b[27]" LOC = U3;
NET "vme_addr_b[26]" LOC = U4;
NET "vme_addr_b[25]" LOC = U5;
NET "vme_addr_b[24]" LOC = V1;
NET "vme_addr_b[23]" LOC = V2;
NET "vme_addr_b[22]" LOC = W1;
NET "vme_addr_b[21]" LOC = W3;
NET "vme_addr_b[20]" LOC = AA4;
NET "vme_addr_b[19]" LOC = AA5;
NET "vme_addr_b[18]" LOC = Y1;
NET "vme_addr_b[17]" LOC = Y2;
NET "vme_addr_b[16]" LOC = Y3;
NET "vme_addr_b[15]" LOC = Y4;
NET "vme_addr_b[14]" LOC = AC1;
NET "vme_addr_b[13]" LOC = AC3;
NET "vme_addr_b[12]" LOC = AD1;
NET "vme_addr_b[11]" LOC = AD2;
NET "vme_addr_b[10]" LOC = AB3;
NET "vme_addr_b[9]" LOC = AB4;
NET "vme_addr_b[8]" LOC = AD3;
NET "vme_addr_b[7]" LOC = AD4;
NET "vme_addr_b[6]" LOC = AC4;
NET "vme_addr_b[5]" LOC = AC5;
NET "vme_addr_b[4]" LOC = N7;
NET "vme_addr_b[3]" LOC = N8;
NET "vme_addr_b[2]" LOC = AE1;
NET "vme_addr_b[1]" LOC = AE3;
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "rst_n_i" LOC = AD28;
NET "clk_20m_vcxo_i" LOC = V26;
#----------------------------------------
# 1-wire thermoeter + unique ID
#----------------------------------------
NET "tempid_dq_b" LOC = AC30;
#===============================================================================
# IO Standard Constraints
#===============================================================================
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_rst_n_i" IOSTANDARD = "LVCMOS33";
#NET "vme_sysclk_i" IOSTANDARD = "LVCMOS33";
NET "vme_retry_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_retry_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_lword_n_b" IOSTANDARD = "LVCMOS33";
NET "vme_iackout_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_iackin_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_iack_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[5]" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_data_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_data_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_berr_o" IOSTANDARD = "LVCMOS33";
NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[6]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[4]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[3]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[2]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[1]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[0]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[2]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[31]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[30]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[29]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[28]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[27]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[26]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[25]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[24]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[23]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[22]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[21]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[20]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[19]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[18]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[17]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[16]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[15]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[14]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[13]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[12]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[11]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[10]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[9]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[8]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[7]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[6]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[5]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[4]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[3]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[2]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[1]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[0]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[5]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[2]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[31]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[30]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[29]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[28]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[27]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[26]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[25]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[24]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[23]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[22]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[21]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[20]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[19]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[18]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[17]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[16]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[15]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[14]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[13]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[12]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[11]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[10]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[9]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[8]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[7]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[6]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[5]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[4]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[3]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[2]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[1]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "rst_n_i" IOSTANDARD = "LVCMOS33";
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# 1-wire thermoeter + unique ID
#----------------------------------------
NET "tempid_dq_b" IOSTANDARD = "LVCMOS33";
NET "fmc1_prsntm2c_n_i" LOC = AE29;
NET "fmc1_scl_b" LOC = W29;
NET "fmc1_sda_b" LOC = V30;
NET "fmc0_prsntm2c_n_i" LOC = N30;
NET "fmc0_scl_b" LOC = P28;
NET "fmc0_sda_b" LOC = P30;
NET "fmc1_prsntm2c_n_i" IOSTANDARD = "LVCMOS33";
NET "fmc1_scl_b" IOSTANDARD = "LVCMOS33";
NET "fmc1_sda_b" IOSTANDARD = "LVCMOS33";
NET "fmc0_prsntm2c_n_i" IOSTANDARD = "LVCMOS33";
NET "fmc0_scl_b" IOSTANDARD = "LVCMOS33";
NET "fmc0_sda_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Timing constraints
#----------------------------------------
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
hdl/top/golden/svec_top.vhd
deleted
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7c4136db
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hdl/top/golden/synthesis_descriptor.vhd
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-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SVEC (Simple VME FMC Carrier) SDB descriptor
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2014-02-04
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SVEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
use
work
.
wishbone_pkg
.
all
;
package
synthesis_descriptor
is
constant
c_sdb_synthesis_info
:
t_sdb_synthesis
:
=
(
syn_module_name
=>
"svec-golden "
,
syn_commit_id
=>
"daf244bfc22002fbf68514441cd45c23"
,
syn_tool_name
=>
"ISE "
,
syn_tool_version
=>
x"00000133"
,
syn_date
=>
x"20140204"
,
syn_username
=>
"twlostow "
);
constant
c_sdb_repo_url
:
t_sdb_repo_url
:
=
(
repo_url
=>
"git://ohwr.org/fmc-projects/svec.git "
);
end
package
synthesis_descriptor
;
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