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Simple VME FMC Carrier SVEC
Commits
72f8d1dd
Commit
72f8d1dd
authored
Nov 14, 2019
by
Tristan Gingold
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svec_vme16: add syn project, modify design.
parent
6d427baa
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4 changed files
with
88 additions
and
61 deletions
+88
-61
Manifest.py
hdl/top/vme16_test/Manifest.py
+5
-5
svec_vme16.ucf
hdl/top/vme16_test/svec_vme16.ucf
+24
-0
svec_vme16.vhd
hdl/top/vme16_test/svec_vme16.vhd
+22
-15
vmecore_test.vhd
hdl/top/vme16_test/vmecore_test.vhd
+37
-41
No files found.
hdl/top/vme16_test/Manifest.py
View file @
72f8d1dd
files
=
[
files
=
[
"svec_vme
core_test_top
.vhd"
,
"svec_vme
16
.vhd"
,
"svec_vme
core_test_top
.ucf"
,
"svec_vme
16
.ucf"
,
"vmecore_test.vhd"
,
"vmecore_test.vhd"
,
]
]
top_module
=
"svec_vme
core_test_top
"
top_module
=
"svec_vme
16
"
target
=
None
target
=
None
fetchto
=
"../../ip_cores"
fetchto
=
"../../ip_cores"
modules
=
{
"git"
:
[
"g
eneral-cores
"
,
modules
=
{
"git"
:
[
"g
it://ohwr.org/project/general-cores.git
"
,
"
vme64x-core
"
]
"
git://ohwr.org/project/vme64x-core.git
"
]
}
}
hdl/top/vme16_test/svec_vme
core_test_top
.ucf
→
hdl/top/vme16_test/svec_vme
16
.ucf
View file @
72f8d1dd
...
@@ -37,21 +37,37 @@ NET "vme_ga_i[2]" LOC = AJ1;
...
@@ -37,21 +37,37 @@ NET "vme_ga_i[2]" LOC = AJ1;
NET "vme_ga_i[1]" LOC = AH1;
NET "vme_ga_i[1]" LOC = AH1;
NET "vme_ga_i[0]" LOC = V7;
NET "vme_ga_i[0]" LOC = V7;
NET "vme_data_b[31]" LOC = AK3;
NET "vme_data_b[31]" LOC = AK3;
NET "vme_data_b[31]" PULLUP;
NET "vme_data_b[30]" LOC = AH3;
NET "vme_data_b[30]" LOC = AH3;
NET "vme_data_b[30]" PULLUP;
NET "vme_data_b[29]" LOC = T8;
NET "vme_data_b[29]" LOC = T8;
NET "vme_data_b[29]" PULLUP;
NET "vme_data_b[28]" LOC = T9;
NET "vme_data_b[28]" LOC = T9;
NET "vme_data_b[28]" PULLUP;
NET "vme_data_b[27]" LOC = AK4;
NET "vme_data_b[27]" LOC = AK4;
NET "vme_data_b[27]" PULLUP;
NET "vme_data_b[26]" LOC = AJ4;
NET "vme_data_b[26]" LOC = AJ4;
NET "vme_data_b[26]" PULLUP;
NET "vme_data_b[25]" LOC = W6;
NET "vme_data_b[25]" LOC = W6;
NET "vme_data_b[25]" PULLUP;
NET "vme_data_b[24]" LOC = W7;
NET "vme_data_b[24]" LOC = W7;
NET "vme_data_b[24]" PULLUP;
NET "vme_data_b[23]" LOC = AB6;
NET "vme_data_b[23]" LOC = AB6;
NET "vme_data_b[23]" PULLUP;
NET "vme_data_b[22]" LOC = AB7;
NET "vme_data_b[22]" LOC = AB7;
NET "vme_data_b[22]" PULLUP;
NET "vme_data_b[21]" LOC = W9;
NET "vme_data_b[21]" LOC = W9;
NET "vme_data_b[21]" PULLUP;
NET "vme_data_b[20]" LOC = W10;
NET "vme_data_b[20]" LOC = W10;
NET "vme_data_b[20]" PULLUP;
NET "vme_data_b[19]" LOC = AK5;
NET "vme_data_b[19]" LOC = AK5;
NET "vme_data_b[19]" PULLUP;
NET "vme_data_b[18]" LOC = AH5;
NET "vme_data_b[18]" LOC = AH5;
NET "vme_data_b[18]" PULLUP;
NET "vme_data_b[17]" LOC = AD6;
NET "vme_data_b[17]" LOC = AD6;
NET "vme_data_b[17]" PULLUP;
NET "vme_data_b[16]" LOC = AC6;
NET "vme_data_b[16]" LOC = AC6;
NET "vme_data_b[16]" PULLUP;
NET "vme_data_b[15]" LOC = AA6;
NET "vme_data_b[15]" LOC = AA6;
NET "vme_data_b[14]" LOC = AA7;
NET "vme_data_b[14]" LOC = AA7;
NET "vme_data_b[13]" LOC = T6;
NET "vme_data_b[13]" LOC = T6;
...
@@ -75,13 +91,21 @@ NET "vme_am_i[2]" LOC = AF4;
...
@@ -75,13 +91,21 @@ NET "vme_am_i[2]" LOC = AF4;
NET "vme_am_i[1]" LOC = AE4;
NET "vme_am_i[1]" LOC = AE4;
NET "vme_am_i[0]" LOC = AK2;
NET "vme_am_i[0]" LOC = AK2;
NET "vme_addr_b[31]" LOC = T2;
NET "vme_addr_b[31]" LOC = T2;
NET "vme_addr_b[31]" PULLUP;
NET "vme_addr_b[30]" LOC = T3;
NET "vme_addr_b[30]" LOC = T3;
NET "vme_addr_b[30]" PULLUP;
NET "vme_addr_b[29]" LOC = T4;
NET "vme_addr_b[29]" LOC = T4;
NET "vme_addr_b[29]" PULLUP;
NET "vme_addr_b[28]" LOC = U1;
NET "vme_addr_b[28]" LOC = U1;
NET "vme_addr_b[28]" PULLUP;
NET "vme_addr_b[27]" LOC = U3;
NET "vme_addr_b[27]" LOC = U3;
NET "vme_addr_b[27]" PULLUP;
NET "vme_addr_b[26]" LOC = U4;
NET "vme_addr_b[26]" LOC = U4;
NET "vme_addr_b[26]" PULLUP;
NET "vme_addr_b[25]" LOC = U5;
NET "vme_addr_b[25]" LOC = U5;
NET "vme_addr_b[25]" PULLUP;
NET "vme_addr_b[24]" LOC = V1;
NET "vme_addr_b[24]" LOC = V1;
NET "vme_addr_b[24]" PULLUP;
NET "vme_addr_b[23]" LOC = V2;
NET "vme_addr_b[23]" LOC = V2;
NET "vme_addr_b[22]" LOC = W1;
NET "vme_addr_b[22]" LOC = W1;
NET "vme_addr_b[21]" LOC = W3;
NET "vme_addr_b[21]" LOC = W3;
...
...
hdl/top/vme16_test/svec_vme
core_test_top
.vhd
→
hdl/top/vme16_test/svec_vme
16
.vhd
View file @
72f8d1dd
...
@@ -47,7 +47,7 @@ use work.vme64x_pkg.all;
...
@@ -47,7 +47,7 @@ use work.vme64x_pkg.all;
library
unisim
;
library
unisim
;
use
unisim
.
vcomponents
.
all
;
use
unisim
.
vcomponents
.
all
;
entity
svec_vme
core_test_top
is
entity
svec_vme
16
is
port
(
port
(
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Clocks/resets
-- Clocks/resets
...
@@ -96,16 +96,17 @@ entity svec_vmecore_test_top is
...
@@ -96,16 +96,17 @@ entity svec_vmecore_test_top is
fp_led_column_o
:
out
std_logic_vector
(
3
downto
0
)
fp_led_column_o
:
out
std_logic_vector
(
3
downto
0
)
);
);
end
entity
svec_vme
core_test_top
;
end
entity
svec_vme
16
;
architecture
top
of
svec_vme
core_test_top
is
architecture
top
of
svec_vme
16
is
-- Wishbone bus from master
-- Wishbone bus from master
signal
master_out
:
t_wishbone_master_out
;
signal
master_out
:
t_wishbone_master_out
;
signal
master_in
:
t_wishbone_master_in
;
signal
master_in
:
t_wishbone_master_in
;
-- VME
-- VME
signal
vme_data_b_out
:
std_logic_vector
(
31
downto
0
);
signal
vme_data_b_out
:
std_logic_vector
(
15
downto
0
);
signal
vme_data_b_out1
:
std_logic_vector
(
31
downto
16
);
signal
vme_addr_b_out
:
std_logic_vector
(
31
downto
1
);
signal
vme_addr_b_out
:
std_logic_vector
(
31
downto
1
);
signal
vme_lword_n_b_out
:
std_logic
;
signal
vme_lword_n_b_out
:
std_logic
;
signal
vme_data_dir_int
:
std_logic
;
signal
vme_data_dir_int
:
std_logic
;
...
@@ -213,14 +214,18 @@ begin -- architecture top
...
@@ -213,14 +214,18 @@ begin -- architecture top
inst_vme_core
:
entity
work
.
xvme64x_core
inst_vme_core
:
entity
work
.
xvme64x_core
generic
map
(
generic
map
(
g_CLOCK_PERIOD
=>
8
,
g_CLOCK_PERIOD
=>
8
,
g_DECODE_AM
=>
True
,
g_VME32
=>
False
,
g_ENABLE_CR_CSR
=>
False
,
g_USER_CSR_EXT
=>
False
,
g_USER_CSR_EXT
=>
False
,
g_WB_GRANULARITY
=>
BYTE
,
g_WB_GRANULARITY
=>
BYTE
,
g_MANUFACTURER_ID
=>
c_CERN_ID
,
g_MANUFACTURER_ID
=>
c_CERN_ID
,
g_BOARD_ID
=>
c_SVEC_ID
,
g_BOARD_ID
=>
c_SVEC_ID
,
g_REVISION_ID
=>
c_SVEC_REVISION_ID
,
g_REVISION_ID
=>
c_SVEC_REVISION_ID
,
g_PROGRAM_ID
=>
c_SVEC_PROGRAM_ID
)
g_PROGRAM_ID
=>
c_SVEC_PROGRAM_ID
,
g_DECODER
=>
(
0
=>
(
adem
=>
x"fff00000"
,
amcap
=>
x"ee000000_00000000"
,
dawpr
=>
x"83"
),
others
=>
(
adem
=>
x"00000000"
,
amcap
=>
x"00000000_00000000"
,
dawpr
=>
x"83"
))
)
port
map
(
port
map
(
clk_i
=>
clk_sys
,
clk_i
=>
clk_sys
,
rst_n_i
=>
local_reset_n
,
rst_n_i
=>
local_reset_n
,
...
@@ -231,8 +236,10 @@ begin -- architecture top
...
@@ -231,8 +236,10 @@ begin -- architecture top
vme_i
.
ds_n
=>
vme_ds_n_i
,
vme_i
.
ds_n
=>
vme_ds_n_i
,
vme_i
.
ga
=>
vme_ga
,
vme_i
.
ga
=>
vme_ga
,
vme_i
.
lword_n
=>
vme_lword_n_b
,
vme_i
.
lword_n
=>
vme_lword_n_b
,
vme_i
.
addr
=>
vme_addr_b
,
vme_i
.
addr
(
23
downto
1
)
=>
vme_addr_b
(
23
downto
1
),
vme_i
.
data
=>
vme_data_b
,
vme_i
.
addr
(
31
downto
24
)
=>
x"00"
,
vme_i
.
data
(
15
downto
0
)
=>
vme_data_b
(
15
downto
0
),
vme_i
.
data
(
31
downto
16
)
=>
x"0000"
,
vme_i
.
iack_n
=>
vme_iack_n_i
,
vme_i
.
iack_n
=>
vme_iack_n_i
,
vme_i
.
iackin_n
=>
vme_iackin_n_i
,
vme_i
.
iackin_n
=>
vme_iackin_n_i
,
vme_o
.
berr_n
=>
vme_berr_n_o
,
vme_o
.
berr_n
=>
vme_berr_n_o
,
...
@@ -240,7 +247,8 @@ begin -- architecture top
...
@@ -240,7 +247,8 @@ begin -- architecture top
vme_o
.
retry_n
=>
vme_retry_n_o
,
vme_o
.
retry_n
=>
vme_retry_n_o
,
vme_o
.
retry_oe
=>
vme_retry_oe_o
,
vme_o
.
retry_oe
=>
vme_retry_oe_o
,
vme_o
.
lword_n
=>
vme_lword_n_b_out
,
vme_o
.
lword_n
=>
vme_lword_n_b_out
,
vme_o
.
data
=>
vme_data_b_out
,
vme_o
.
data
(
15
downto
0
)
=>
vme_data_b_out
,
vme_o
.
data
(
31
downto
16
)
=>
vme_data_b_out1
,
vme_o
.
addr
=>
vme_addr_b_out
,
vme_o
.
addr
=>
vme_addr_b_out
,
vme_o
.
irq_n
=>
vme_irq_n_o
,
vme_o
.
irq_n
=>
vme_irq_n_o
,
vme_o
.
iackout_n
=>
vme_iackout_n_o
,
vme_o
.
iackout_n
=>
vme_iackout_n_o
,
...
@@ -255,14 +263,13 @@ begin -- architecture top
...
@@ -255,14 +263,13 @@ begin -- architecture top
vme_ga
<=
vme_gap_i
&
vme_ga_i
;
vme_ga
<=
vme_gap_i
&
vme_ga_i
;
-- VME tri-state buffers
-- VME tri-state buffers
vme_data_b
<=
vme_data_b_out
when
vme_data_dir_int
=
'1'
vme_data_b
(
15
downto
0
)
<=
vme_data_b_out
when
vme_data_dir_int
=
'1'
else
(
others
=>
'Z'
);
else
(
others
=>
'Z'
);
vme_addr_b
<=
vme_addr_b_out
when
vme_addr_dir_int
=
'1'
vme_data_b
(
31
downto
0
)
<=
(
others
=>
'Z'
);
else
(
others
=>
'Z'
);
vme_addr_b
<=
(
others
=>
'Z'
);
vme_lword_n_b
<=
vme_lword_n_b_out
when
vme_addr_dir_int
=
'1'
vme_lword_n_b
<=
'Z'
;
else
'Z'
;
vme_addr_dir_o
<=
vme_addr_dir_int
;
vme_addr_dir_o
<=
'0'
;
vme_data_dir_o
<=
vme_data_dir_int
;
vme_data_dir_o
<=
vme_data_dir_int
;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
...
...
hdl/top/vme16_test/vmecore_test.vhd
View file @
72f8d1dd
...
@@ -49,35 +49,36 @@ entity vmecore_test is
...
@@ -49,35 +49,36 @@ entity vmecore_test is
end
vmecore_test
;
end
vmecore_test
;
architecture
rtl
of
vmecore_test
is
architecture
rtl
of
vmecore_test
is
-- Memory map (WB addresses, multiply by 4 to get VME addresses):
-- Memory map:
-- 0 - 0x1ff: sram (512*4B)
-- 0x000 - 0x3ff: sram (512*2B)
-- 0x1000: leds (4B)
-- 0x400: leds (4B)
-- 0x1001: last WB transaction (see the code for the format)
-- 0x401: last WB transaction (see the code for the format)
-- 0x1002: nbr of WB read accesses (write to clear)
-- 0x402: nbr of WB read accesses (write to clear)
-- 0x1003: nbr of WB write accesses (likewise)
-- 0x403: nbr of WB write accesses (likewise)
-- 0x1004: nbr of write errors in pattern ram
-- 0x404: nbr of write errors in pattern ram
-- 0x1005: generates bus error.
-- 0x405: generates bus error.
-- 0x2000: counter (4B). Generate an interrupt when 0 is reached.
-- 0x800: counter (2B). Generate an interrupt when 0 is reached.
-- 0x3000: pattern ram (0x1000 * 4B)
-- 0xc00: pattern ram (0x1000 * 4B)
-- 0x4000 - 0x3ff000: pattern ram
signal
counter
:
unsigned
(
15
downto
0
);
signal
counter
:
unsigned
(
31
downto
0
);
signal
leds
:
std_logic_vector
(
15
downto
0
);
signal
leds
:
std_logic_vector
(
15
downto
0
);
signal
last_trans
:
std_logic_vector
(
28
downto
0
);
signal
last_trans
:
std_logic_vector
(
28
downto
0
);
signal
nbr_read
:
unsigned
(
15
downto
0
);
signal
nbr_read
:
unsigned
(
15
downto
0
);
signal
nbr_write
:
unsigned
(
15
downto
0
);
signal
nbr_write
:
unsigned
(
15
downto
0
);
signal
nbr_write_errors
:
unsigned
(
31
downto
0
);
signal
nbr_write_errors
:
unsigned
(
15
downto
0
);
signal
pattern
:
std_logic_vector
(
31
downto
0
);
signal
pattern
:
std_logic_vector
(
15
downto
0
);
type
sram_type
is
array
(
0
to
16
#
1
ff
#
)
of
std_logic_vector
(
31
downto
0
);
type
sram_type
is
array
(
0
to
16
#
1
ff
#
)
of
std_logic_vector
(
15
downto
0
);
signal
sram
:
sram_type
;
signal
sram
:
sram_type
:
=
(
0
=>
x"0123"
,
1
=>
x"4567"
,
2
=>
x"89ab"
,
others
=>
x"0000"
)
;
begin
begin
-- Pattern of the pattern ram.
-- Pattern of the pattern ram.
pattern
(
31
downto
16
)
<=
not
slave_i
.
adr
(
15
downto
0
);
pattern
(
15
downto
8
)
<=
not
slave_i
.
adr
(
7
downto
0
);
pattern
(
15
downto
0
)
<=
slave_i
.
adr
(
15
downto
0
);
pattern
(
7
downto
0
)
<=
slave_i
.
adr
(
7
downto
0
);
slave_o
.
dat
(
31
downto
16
)
<=
(
others
=>
'0'
);
process
(
clk_sys_i
)
process
(
clk_sys_i
)
procedure
pattern_write
procedure
pattern_write
...
@@ -85,7 +86,7 @@ begin
...
@@ -85,7 +86,7 @@ begin
variable
err
:
boolean
;
variable
err
:
boolean
;
begin
begin
err
:
=
false
;
err
:
=
false
;
for
i
in
3
downto
0
loop
for
i
in
1
downto
0
loop
if
slave_i
.
sel
(
i
)
=
'1'
if
slave_i
.
sel
(
i
)
=
'1'
and
(
slave_i
.
dat
(
8
*
i
+
7
downto
8
*
i
)
/=
and
(
slave_i
.
dat
(
8
*
i
+
7
downto
8
*
i
)
/=
pattern
(
8
*
i
+
7
downto
8
*
i
))
pattern
(
8
*
i
+
7
downto
8
*
i
))
...
@@ -117,7 +118,7 @@ begin
...
@@ -117,7 +118,7 @@ begin
end
if
;
end
if
;
if
slave_i
.
stb
=
'1'
and
slave_i
.
cyc
=
'1'
then
if
slave_i
.
stb
=
'1'
and
slave_i
.
cyc
=
'1'
then
if
slave_i
.
adr
(
1
3
downto
12
)
=
"00"
then
if
slave_i
.
adr
(
1
1
downto
10
)
=
"00"
then
-- Save transaction (very cheap scope).
-- Save transaction (very cheap scope).
last_trans
(
23
downto
0
)
<=
slave_i
.
adr
(
23
downto
0
);
last_trans
(
23
downto
0
)
<=
slave_i
.
adr
(
23
downto
0
);
last_trans
(
27
downto
24
)
<=
slave_i
.
sel
;
last_trans
(
27
downto
24
)
<=
slave_i
.
sel
;
...
@@ -128,17 +129,17 @@ begin
...
@@ -128,17 +129,17 @@ begin
-- Write
-- Write
nbr_write
<=
nbr_write
+
1
;
nbr_write
<=
nbr_write
+
1
;
if
slave_i
.
adr
(
25
downto
14
)
=
x"000"
then
if
slave_i
.
adr
(
25
downto
14
)
=
x"000"
then
case
slave_i
.
adr
(
1
3
downto
12
)
is
case
slave_i
.
adr
(
1
1
downto
10
)
is
when
"00"
=>
when
"00"
=>
idx
:
=
to_integer
(
unsigned
(
slave_i
.
adr
(
8
downto
0
)));
idx
:
=
to_integer
(
unsigned
(
slave_i
.
adr
(
9
downto
1
)));
for
i
in
3
downto
0
loop
for
i
in
1
downto
0
loop
if
slave_i
.
sel
(
i
)
=
'1'
then
if
slave_i
.
sel
(
i
)
=
'1'
then
sram
(
idx
)(
8
*
i
+
7
downto
8
*
i
)
<=
sram
(
idx
)(
8
*
i
+
7
downto
8
*
i
)
<=
slave_i
.
dat
(
8
*
i
+
7
downto
8
*
i
);
slave_i
.
dat
(
8
*
i
+
7
downto
8
*
i
);
end
if
;
end
if
;
end
loop
;
end
loop
;
when
"01"
=>
when
"01"
=>
case
slave_i
.
adr
(
2
downto
0
)
is
case
slave_i
.
adr
(
3
downto
1
)
is
when
"000"
=>
when
"000"
=>
for
i
in
1
downto
0
loop
for
i
in
1
downto
0
loop
if
slave_i
.
sel
(
i
)
=
'1'
then
if
slave_i
.
sel
(
i
)
=
'1'
then
...
@@ -160,7 +161,7 @@ begin
...
@@ -160,7 +161,7 @@ begin
null
;
null
;
end
case
;
end
case
;
when
"10"
=>
when
"10"
=>
for
i
in
3
downto
0
loop
for
i
in
1
downto
0
loop
if
slave_i
.
sel
(
i
)
=
'1'
then
if
slave_i
.
sel
(
i
)
=
'1'
then
counter
(
8
*
i
+
7
downto
8
*
i
)
<=
counter
(
8
*
i
+
7
downto
8
*
i
)
<=
unsigned
(
slave_i
.
dat
(
8
*
i
+
7
downto
8
*
i
));
unsigned
(
slave_i
.
dat
(
8
*
i
+
7
downto
8
*
i
));
...
@@ -171,47 +172,42 @@ begin
...
@@ -171,47 +172,42 @@ begin
when
others
=>
when
others
=>
null
;
null
;
end
case
;
end
case
;
else
pattern_write
;
end
if
;
end
if
;
slave_o
.
ack
<=
'1'
;
slave_o
.
ack
<=
'1'
;
else
else
-- Read
-- Read
nbr_read
<=
nbr_read
+
1
;
nbr_read
<=
nbr_read
+
1
;
if
slave_i
.
adr
(
2
5
downto
14
)
=
x"
000"
then
if
slave_i
.
adr
(
2
3
downto
12
)
=
b"0000_0000_0
000"
then
case
slave_i
.
adr
(
1
3
downto
12
)
is
case
slave_i
.
adr
(
1
1
downto
10
)
is
when
"00"
=>
when
"00"
=>
idx
:
=
to_integer
(
unsigned
(
slave_i
.
adr
(
8
downto
0
)));
idx
:
=
to_integer
(
unsigned
(
slave_i
.
adr
(
9
downto
1
)));
slave_o
.
dat
<=
sram
(
idx
);
slave_o
.
dat
(
15
downto
0
)
<=
sram
(
idx
);
when
"01"
=>
when
"01"
=>
case
slave_i
.
adr
(
2
downto
0
)
is
case
slave_i
.
adr
(
3
downto
1
)
is
when
"000"
=>
when
"000"
=>
slave_o
.
dat
(
31
downto
16
)
<=
(
others
=>
'0'
);
slave_o
.
dat
(
15
downto
0
)
<=
leds
;
slave_o
.
dat
(
15
downto
0
)
<=
leds
;
when
"001"
=>
when
"001"
=>
slave_o
.
dat
<=
(
31
downto
29
=>
'0'
)
&
last_trans
;
slave_o
.
dat
(
15
downto
0
)
<=
last_trans
(
15
downto
0
)
;
when
"010"
=>
when
"010"
=>
slave_o
.
dat
(
31
downto
16
)
<=
(
others
=>
'0'
);
slave_o
.
dat
(
15
downto
0
)
<=
std_logic_vector
(
nbr_read
);
slave_o
.
dat
(
15
downto
0
)
<=
std_logic_vector
(
nbr_read
);
when
"011"
=>
when
"011"
=>
slave_o
.
dat
(
31
downto
16
)
<=
(
others
=>
'0'
);
slave_o
.
dat
(
15
downto
0
)
<=
std_logic_vector
(
nbr_write
);
slave_o
.
dat
(
15
downto
0
)
<=
std_logic_vector
(
nbr_write
);
when
"100"
=>
when
"100"
=>
slave_o
.
dat
<=
std_logic_vector
(
nbr_write_errors
);
slave_o
.
dat
(
15
downto
0
)
<=
std_logic_vector
(
nbr_write_errors
);
when
"101"
=>
when
"101"
=>
slave_o
.
err
<=
'1'
;
slave_o
.
err
<=
'1'
;
when
others
=>
when
others
=>
null
;
null
;
end
case
;
end
case
;
when
"10"
=>
when
"10"
=>
slave_o
.
dat
<=
std_logic_vector
(
counter
);
slave_o
.
dat
(
15
downto
0
)
<=
std_logic_vector
(
counter
);
when
"11"
=>
when
"11"
=>
slave_o
.
dat
<=
pattern
;
slave_o
.
dat
(
15
downto
0
)
<=
pattern
;
when
others
=>
when
others
=>
null
;
null
;
end
case
;
end
case
;
else
else
slave_o
.
dat
<=
pattern
;
slave_o
.
dat
(
15
downto
0
)
<=
pattern
;
end
if
;
end
if
;
slave_o
.
ack
<=
'1'
;
slave_o
.
ack
<=
'1'
;
end
if
;
end
if
;
...
...
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