Commit 6d5ed099 authored by Federico Vaga's avatar Federico Vaga

Merge branch '4-copy-relevant-documentation-from-texi-to-sphinx' into 'master'

Resolve "copy relevant documentation from texi to sphinx"

Closes #4

See merge request be-cem-edl/fec/hardware-modules/svec!5
parents 9ce97270 0c0e62ec
......@@ -4,4 +4,6 @@
_build
*.man
*.html
*.pdf
\ No newline at end of file
*.pdf
svec_xloader_regs.rst
svec_base_regs.rst
......@@ -4,14 +4,16 @@
CHEBY ?= cheby
CHEBY_FILES := svec_base_regs.cheby
CHEBY_FILES += svec_xloader_regs.cheby
CHEBY_DOC_FILES := $(CHEBY_FILES:.cheby=.rst)
all: cheby_doc
vpath %.cheby ../hdl/rtl
vpath %.cheby ../hdl/rtl ../hdl/rtl/bootloader
cheby_doc: $(CHEBY_DOC_FILES)
$(CHEBY_DOC_FILES): %.rst: %.cheby
$(CHEBY) -i $< --gen-doc --doc rest > $@
$(CHEBY) -i $< --gen-doc --doc rest --rest-headers '#~^' | sed -e "1,3d" > $@
clean:
@rm -f $(CHEBY_DOC_FILES)
......
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -56,7 +56,7 @@ master_doc = 'index'
#
# This is also used if you do content translation via gettext catalogs.
# Usually you set "language" from the command line for these cases.
language = None
language = "en"
# List of patterns, relative to source directory, that match files and
# directories to ignore when looking for source files.
......
*.texi
git_revision.in
*.txt
*.pdf
Backup_*.cdr
*.wmf
\ No newline at end of file
#
# Makefile for the documentation directory
#
# Copyright 1994,2000,2010,2011 Alessandro Rubini <rubini@linux.it>
#
#################
# There is not basenames here, all *.in are considered input
INPUT = svec-gateware-manual.in
TEXI = $(INPUT:.in=.texi)
INFO = $(INPUT:.in=.info)
HTML = $(INPUT:.in=.html)
TXT = $(INPUT:.in=.txt)
PDF = $(INPUT:.in=.pdf)
ALL = $(PDF)
MAKEINFO ?= makeinfo
%.texi: %.in
@rm -f $@
sed -f ./infofilter $< > $@
emacs -batch --no-site-file -l fixinfo $@
chmod -w $@
#%.info: %.texi
# $(MAKEINFO) $< -o $@
#%.html: %.texi
# $(MAKEINFO) --html --no-split -o $@ $<
%.txt: %.texi
$(MAKEINFO) --no-headers $< > $@
%.pdf: %.texi
texi2pdf --batch $<
##############################################
.PHONY: all images check terse clean install
.INTERMEDIATE: $(TEXI)
all: images $(ALL)
$(MAKE) terse
images::
if [ -d images ]; then $(MAKE) -C images || exit 1; fi
check: _err.ps
gs -sDEVICE=linux -r320x200x16 $<
terse:
for n in cp fn ky pg toc tp vr aux log; do rm -f *.$$n; done
rm -f *~
clean: terse
rm -f $(ALL) $(TEXI)
install:
#!/bin/bash
cd drawings; find . -name "*.eps" | xargs -n 1 epstopdf; cd ..
REVISION=`git describe HEAD`
echo "@set git-revision $REVISION" > git_revision.in
make clean && make
evince svec-gateware-manual.pdf
\ No newline at end of file
This diff is collapsed.
This diff is collapsed.
;; use:
;; emacs -batch -l ./fixinfo.el <file>
;; or, better:
;; emacs -batch --no-site-file -l ./fixinfo.el <file>
(defun fixinfo (file)
(find-file-other-window file)
(message (concat "Maxing texinfo tree in " file))
(texinfo-all-menus-update)
(texinfo-every-node-update)
(save-buffer)
(kill-buffer (current-buffer))
)
;; loop over command line arguments
(mapcar 'fixinfo command-line-args-left)
(kill-emacs)
@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{CSR} @tab
Control/Status reg
@item @code{0x4} @tab
REG @tab
@code{I2CR0} @tab
I2C bitbanged IO register for mezzanine 0
@item @code{0x8} @tab
REG @tab
@code{I2CR1} @tab
I2C bitbanged IO register for mezzanine 1
@item @code{0xc} @tab
REG @tab
@code{I2CR2} @tab
I2C bitbanged IO register for mezzanine 2
@item @code{0x10} @tab
REG @tab
@code{I2CR3} @tab
I2C bitbanged IO register for mezzanine 3
@end multitable
@regsection @code{CSR} - Control/Status reg
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{3...0}
@tab R/O @tab
@code{SLOT_COUNT}
@tab @code{X} @tab
Number of FMC slots
@item @code{7...4}
@tab R/O @tab
@code{FMC_PRESENT}
@tab @code{X} @tab
FMC presence line status
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{SLOT_COUNT} @tab Number of FMC slots provided by this carrier
@item @code{FMC_PRESENT} @tab State of presence lines in the respective slots (1 = mezzanine inserted). Bit N = mezzanine (N+1).
@end multitable
@regsection @code{I2CR0} - I2C bitbanged IO register for mezzanine 0
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{SCL_OUT}
@tab @code{1} @tab
SCL Line out
@item @code{1}
@tab R/W @tab
@code{SDA_OUT}
@tab @code{1} @tab
SDA Line out
@item @code{2}
@tab R/O @tab
@code{SCL_IN}
@tab @code{X} @tab
SCL Line in
@item @code{3}
@tab R/O @tab
@code{SDA_IN}
@tab @code{X} @tab
SDA Line in
@end multitable
@regsection @code{I2CR1} - I2C bitbanged IO register for mezzanine 1
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{SCL_OUT}
@tab @code{1} @tab
SCL Line out
@item @code{1}
@tab R/W @tab
@code{SDA_OUT}
@tab @code{1} @tab
SDA Line out
@item @code{2}
@tab R/O @tab
@code{SCL_IN}
@tab @code{X} @tab
SCL Line in
@item @code{3}
@tab R/O @tab
@code{SDA_IN}
@tab @code{X} @tab
SDA Line in
@end multitable
@regsection @code{I2CR2} - I2C bitbanged IO register for mezzanine 2
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{SCL_OUT}
@tab @code{1} @tab
SCL Line out
@item @code{1}
@tab R/W @tab
@code{SDA_OUT}
@tab @code{1} @tab
SDA Line out
@item @code{2}
@tab R/O @tab
@code{SCL_IN}
@tab @code{X} @tab
SCL Line in
@item @code{3}
@tab R/O @tab
@code{SDA_IN}
@tab @code{X} @tab
SDA Line in
@end multitable
@regsection @code{I2CR3} - I2C bitbanged IO register for mezzanine 3
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{SCL_OUT}
@tab @code{1} @tab
SCL Line out
@item @code{1}
@tab R/W @tab
@code{SDA_OUT}
@tab @code{1} @tab
SDA Line out
@item @code{2}
@tab R/O @tab
@code{SCL_IN}
@tab @code{X} @tab
SCL Line in
@item @code{3}
@tab R/O @tab
@code{SDA_IN}
@tab @code{X} @tab
SDA Line in
@end multitable
#! /usr/bin/sed -f
# allow "%" as a comment char, but only at the beginning of the line
s/^%/@c /
#s/[^\\]%.*$//
s/^\\%/%/
#preserve blanks and braces in @example blocks
/@example/,/@end example/ s/{/@{/g
/@example/,/@end example/ s/}/@}/g
/@example/,/@end example/ p
/@example/,/@end example/ d
/@smallexample/,/@end smallexample/ s/{/@{/g
/@smallexample/,/@end smallexample/ s/}/@}/g
/@smallexample/,/@end smallexample/ p
/@smallexample/,/@end smallexample/ d
# remove leading blanks
s/^[ ]*//
This diff is collapsed.
@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{CSR} @tab
Control/status register
@item @code{0x4} @tab
REG @tab
@code{BTRIGR} @tab
Bootloader Trigger Register
@item @code{0x8} @tab
REG @tab
@code{FAR} @tab
Flash Access Register
@item @code{0xc} @tab
REG @tab
@code{IDR} @tab
ID Register
@item @code{0x10} @tab
FIFOREG @tab
@code{FIFO_R0} @tab
FIFO 'Bitstream FIFO' data input register 0
@item @code{0x14} @tab
FIFOREG @tab
@code{FIFO_R1} @tab
FIFO 'Bitstream FIFO' data input register 1
@item @code{0x18} @tab
REG @tab
@code{FIFO_CSR} @tab
FIFO 'Bitstream FIFO' control/status register
@end multitable
@regsection @code{CSR} - Control/status register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab W/O @tab
@code{START}
@tab @code{0} @tab
Start configuration
@item @code{1}
@tab R/O @tab
@code{DONE}
@tab @code{X} @tab
Configuration done
@item @code{2}
@tab R/O @tab
@code{ERROR}
@tab @code{X} @tab
Configuration error
@item @code{3}
@tab R/O @tab
@code{BUSY}
@tab @code{X} @tab
Loader busy
@item @code{4}
@tab R/W @tab
@code{MSBF}
@tab @code{0} @tab
Byte order select
@item @code{5}
@tab W/O @tab
@code{SWRST}
@tab @code{0} @tab
Software resest
@item @code{6}
@tab W/O @tab
@code{EXIT}
@tab @code{0} @tab
Exit bootloader mode
@item @code{13...8}
@tab R/W @tab
@code{CLKDIV}
@tab @code{0} @tab
Serial clock divider
@item @code{21...14}
@tab R/O @tab
@code{VERSION}
@tab @code{X} @tab
Bootloader version
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{START} @tab write 1: starts the configuration process.@* write 0: no effect
@item @code{DONE} @tab read 1: the bitstream has been loaded@* read 0: configuration still in progress
@item @code{ERROR} @tab read 1: an error occured during the configuration (DONE/INIT_B timeout)@* read 0: configuration was successful
@item @code{BUSY} @tab read 1: the loader is busy (can't start configuration yet)@* read 0: the loader is ready to re-configure the FPGA
@item @code{MSBF} @tab write 1: MSB first (big endian host)@* write 0: LSB first (little endian host)
@item @code{SWRST} @tab write 1: resets the loader core@* write 0: no effect
@item @code{EXIT} @tab write 1: terminate bootloader mode and go passive (VME only)
@item @code{CLKDIV} @tab CCLK division ratio. CCLK frequency = F_sysclk / 2 / (CLKDIV + 1)
@end multitable
@regsection @code{BTRIGR} - Bootloader Trigger Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{7...0}
@tab W/O @tab
@code{BTRIGR}
@tab @code{0} @tab
Trigger Sequence Input
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{BTRIGR} @tab Write a sequence of 0xde, 0xad, 0xbe, 0xef, 0xca, 0xfe, 0xba, 0xbe to enter bootloader mode (VME only)
@end multitable
@regsection @code{FAR} - Flash Access Register
Provides direct access to the SPI flash memory containing the bitstream.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{7...0}
@tab R/W @tab
@code{DATA}
@tab @code{X} @tab
SPI Data
@item @code{8}
@tab R/W @tab
@code{XFER}
@tab @code{0} @tab
SPI Start Transfer
@item @code{9}
@tab R/O @tab
@code{READY}
@tab @code{X} @tab
SPI Ready
@item @code{10}
@tab R/W @tab
@code{CS}
@tab @code{0} @tab
SPI Chip Select
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{DATA} @tab Data to be written / read to/from the flash SPI controller.
@item @code{XFER} @tab write 1: initiate an SPI transfer with an 8-bit data word taken from the @code{DATA}field@* write 0: no effect
@item @code{READY} @tab read 1: Core is ready to initiate another transfer. DATA field contains the data read during previous transaction.@*read 0: core is busy
@item @code{CS} @tab write 1: Enable target SPI controller@*write 0: Disable target SPI controller
@end multitable
@regsection @code{IDR} - ID Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{IDR}
@tab @code{X} @tab
Identification code
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{IDR} @tab User-defined identification code (g_idr_value generic)
@end multitable
@regsection @code{FIFO_R0} - FIFO 'Bitstream FIFO' data input register 0
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{1...0}
@tab W/O @tab
@code{XSIZE}
@tab @code{0} @tab
Entry size
@item @code{2}
@tab W/O @tab
@code{XLAST}
@tab @code{0} @tab
Last xfer
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{XSIZE} @tab Number of bytes to send (0 = 1 byte .. 3 = full 32-bit word)
@item @code{XLAST} @tab write 1: indicates the last word to be written to the FPGA
@end multitable
@regsection @code{FIFO_R1} - FIFO 'Bitstream FIFO' data input register 1
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{XDATA}
@tab @code{0} @tab
Data
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{XDATA} @tab Subsequent words of the bitstream
@end multitable
@regsection @code{FIFO_CSR} - FIFO 'Bitstream FIFO' control/status register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{16}
@tab R/O @tab
@code{FULL}
@tab @code{X} @tab
FIFO full flag
@item @code{17}
@tab R/O @tab
@code{EMPTY}
@tab @code{X} @tab
FIFO empty flag
@item @code{18}
@tab W/O @tab
@code{CLEAR_BUS}
@tab @code{0} @tab
FIFO clear
@item @code{7...0}
@tab R/O @tab
@code{USEDW}
@tab @code{X} @tab
FIFO counter
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{full} @tab 1: FIFO 'Bitstream FIFO' is full@*0: FIFO is not full
@item @code{empty} @tab 1: FIFO 'Bitstream FIFO' is empty@*0: FIFO is not empty
@item @code{clear_bus} @tab write 1: clears FIFO 'Bitstream FIFO@*write 0: no effect
@item @code{usedw} @tab Number of data records currently being stored in FIFO 'Bitstream FIFO'
@end multitable
..
SPDX-License-Identifier: CC-BY-SA-4.0
SPDX-FileCopyrightText: 2019-2020 CERN
The SVEC Bootloader
===================
The System FPGA bootloader allows to boot the Application FPGA from the VME bus or from the onboard Flash memory and reprogram both the System and Application bitstreams in the flash via VME (see @ref{fig:boot_modes}). The boot process goes as follows:
#. Power up,
#. SFPGA checks for presence of a valid bitstream file for the Application FPGA in the Flash memory,
#. if a valid bitstream has been found, the AFPGA is initialized with it,
#. if not, the Bootloader enters passive mode. Upon reception of a boot sequence, if gives access to the Flash for the host or lets it program the AFPGA directly.
.. figure:: bootloader.svg
Boot modes of the SVEC card
Bootloader versions
-------------------
There are three versions of the bootloader in use:
- **Version 1** which only allows booting the Application FPGA via VME (no flash
support). This version of the bootloader has been programmed in older SVEC
cards. If the VME flasher (``svec-flasher``) tool is unable to detect the
flash memory, you're likely running the old bootloader.
- **Version 2** which supports everything described in this manual except for
providing SPI flash access to the AFPGA.
- **Version 3** which supports everything described in this manual, including
accessing the SPI flash from the AFPGA.
The new version is software-compatible with the old one, there is no need to update any drivers. The register description applies to both versions, except that for the version 1, the Flash Access Register (``FAR``) is not functional.
.. note:: When possible update to the latest version
.. note:: Following documentation assumes version 3
VME Interface
-------------
The bootloader core supports only 32-bit data CR/CSR accesses from/to address
range ``0x70000 - 0x70020``, allowing for plug&play reprogramming of the cards
only knowing their physical slot locations. All other transfers are ignored. The
base address is ``0x70000``, and corresponds to the ``CSR`` register. When the
card is powered up, the VME interface stays in passive mode, monitoring VME
accesses without ACKing them. This is to prevent conflicts with the CR/CSR space
of the VME core in the Application FPGA. To access the bootloader VME interface,
one needs to write the magic sequence of 8 following transfers: ``0xde``,
``0xad``, ``0xbe``, ``0xef``, ``0xca``, ``0xfe``, ``0xba``, ``0xbe`` to the
``BTRIGR`` register (for register definitions, @pxref{System FPGA Register
Map``).
Entering Bootloader Mode
~~~~~~~~~~~~~~~~~~~~~~~~
To check if the bootloader has been activated, read the ``IDR`` register. It
should be equal to ``SVEC`` ASCII string encoded in HEX. Any other value
indicates that the boot trigger sequence was not correctly recognized, the
System FPGA is unprogrammed, the geographical address of the card is wrong or
that the card itself is faulty.
.. note:: Triggering bootloader mode causes automatic reset (un-programming) of
the Application FPGA.
.. note:: Since the bootloader core supports only 32-bit transfers, one must
extend the magic values with zeroes (e.g. ``0x000000de``, etc.) and
write full 32-bit words. Attempts to write the magic sequence as
single bytes (D8 transfer mode) will be ignored.
.. note:: Trigger sequence must not be interleaved with other accesses to the
bootloader address range of the same card.
.. note:: Write operations to ``BTRIGR`` register while the bootloader is in
passive mode will not be acknowledged on the VME bus and may sometimes
cause bus errors to be reported by the host VME driver. They are not
harmful, though.
Programming the AFPGA
~~~~~~~~~~~~~~~~~~~~~
Programming the Application FPGA directly via VME involves the following steps:
#. Reset the Xilinx Passive Serial boot interface by writing the ``CSR.SWRST`` bit,
#. Set download speed by writing the ``CSR.CLKDIV`` field. Default value is ``1``,
#. Write the ``CSR.START`` bit and set endianness via the ``CSR.MSBF`` bit,
#. Write the bitstream to the FIFO registers, observing FIFO full/empty status.
The last transfer should have ``FIFO_R1.XLAST`` bit set to 1,
#. Wait for assertion of ``CSR.DONE``. ``CSR.ERROR`` bit indicates a problem
during configuration (most likely, an invalid bitstream),
#. Exit bootloader mode by writing 1 to ``CSR.EXIT`` bit.
A code example is available in the repository (@pxref{repo_link,,3}). Successful gateware download to the Application FPGA is indicated by turning on the ``AFPGA DONE`` LED in the middle of the PCB.
Programming The Flash
---------------------
The bootloader also allows raw access to the Flash memory (`M25P128`_ or `MT25QL128`_
in newer SVEC cards) via the ``FAR`` register. Low-level details about programming the Flash memories can be found in their datasheets.
.. note:: It is advised to protect the region of the flash containing the system
FPGA bitstream from being accidentally overwritten, as this will
result in rendering the card unusable and will require re-programming
the flash via JTAG. Details on memory protection can be found in the
Flash memory datasheet.
.. note:: The freshly-programmed bitstreams will be loaded into the FPGAs after
power-cycling the card. In order to avoid the power cycle, one can
boot the Application FPGA directly using the same bitstream.
.. _`M25P128`: http://www.micron.com/parts/nor-flash/serial-nor-flash/m25p128-vme6gb
.. _`MT25QL128`: https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qlhs_l_128_aba_0.pdf
The ``svec-flasher``
~~~~~~~~~~~~~~~~~~~~
The tool ``software/tools/vme-flasher/svec-flasher`` accesses the VME interface
to program the SPI flash with a bitstream (``.bin`` format) targeting the AFPGA.
With the option ``-b``, it is also possible to program the SPI flash with a
bootloader bitstream. Finally, with the option ``-f``, it is possible to program
directly the AFPGA.
.. warning:: Before programming the flash, please unload the SVEC kernel driver
using ``rmmod svec-fmc-carrier``
.. warning:: Programming incorrect bootloader bitstream or a failure of
bootloader update process will render your card unusable. In such
case, the card can be recovered by programming the bootloader
through JTAG. The flasher tool asks for additional confirmation
before reprogramming the memory.
.. note:: The card must be rebooted for the new bitstream to be loaded to the
Application FPGA.
Updating the bootloader through JTAG
-------------------------------------
If you have the bootloader version 1 or 2, or you corrupted the SPI flash, then
JTAG is your only option to program the SPI flash with the latest bootloader
version. The procedure goes as follows.
#. Download the latest bootloader ``svec-bootloader-[latest release].mcs`` from
`Release <http://www.ohwr.org/projects/svec/wiki/Releases>`_.
#. Connect Xilinx JTAG programmer to the JTAG connector of the card to be
updated.
#. Launch ISE iMPACT.
#. Double-Click ``Boundary Scan`` in the left pane (``iMPACT flows``).
#. Open the right-click menu in the main work area and select ``Initialize
chain`` or press ``Ctrl+I``.
#. Right click on the ``SPI/BPI ?`` box above the ``xc6slx9`` FPGA and select
``Add SPI/BPI Flash``.
#. Pick the ``svec-bootloader-[latest release].mcs`` file.
#. Select flash type: SPI PROM, M25P128 (or N25Q128 if you have a newer SVEC
with a MT25QL128 Flash memory chip), data width: 1.
#. Right click on the ``FLASH`` chip above the ``xc6slx9`` and select
``Program``. Select the ``Verify`` option and click OK.
#. If everything went fine, ``Programming succeeded`` message will appear.
#. Reboot the VME crate to use the new bootloader.
.. note:: Updating the bootloader does not require updating the drivers, as it
is backwards-compatible.
Memory Map
----------
.. include:: svec_xloader_regs.rst
......@@ -15,7 +15,6 @@ develop SPEC based designs.
The ``SPEC base`` is compliant with the `FPGA device identification`_ rules.
Components
----------
......@@ -23,16 +22,16 @@ The following table summarizes the ``SVEC base`` components and after that
you have a brief description of each of them. We do not expect to add or
remove components in the future so this should be an exhaustive list.
=================== ============ ========== =============
Component Start End Cap. Mask Bit
CSR 0x00000040 0x0000005F (Mandatory)
Therm. & ID 0x00000070 0x0000007F 1
Gen-Core I2C Ocore 0x00000080 0x0000009F (Mandatory)
Gen-Core SPI 0x000000A0 0x000000BF 2
Gen-Core VIC 0x00000100 0x000001FF 0
Build info 0x00000200 0x000002FF 4
White-Rabbit 0x00001000 0x00001FFF 3
=================== ============ ========== =============
=================== =============
Component Cap. Mask Bit
CSR (Mandatory)
Therm. & ID 1
Gen-Core I2C Ocore (Mandatory)
Gen-Core SPI 2
Gen-Core VIC 0
Build info 4
White-Rabbit 3
=================== =============
.. note::
The *Capability Mask Bit* (Cap. Mask Bit) refers to the bit in the
......@@ -113,6 +112,27 @@ Memory Map
.. include:: svec_base_regs.rst
SVEC Golden FPGA bitstream
--------------------------
The SVEC Application FPGA golden bitstream is a safe FPGA application
instantiating only the `SVEC Base HDL Component`_. This enables all SVEC
hardware features allowing users to perform basic actions:
- reading the card temperature,
- accessing the on-board SPI flash,
- verify the presence of an FMC module,
- accessing the FMC module's EEPROM,
- get a working white-rabbit link.
.. note:: You might find this bitstream pre-programmed on your card
.. note:: The bitstream does not drive any of the FMC module user/clock pins to
protect from electrical damage resulting from mismatched I/O standards.
.. note:: SVEC base memory map is instanciated at the beginning of the address
space. Hence, `Memory Map`_ is the same.
.. _`SVEC project`: https://ohwr.org/project/svec
.. _`FPGA device identification`: https://www.ohwr.org/project/fpga-dev-id/
.. _`general cores`: https://www.ohwr.org/projects/general-cores
......
.. SPDX-License-Identifier: CC-BY-SA-4.0
.. SPDX-FileCopyrightText: 2019-2020 CERN
The SPI FLASH Memory
====================
The on-board SPI flash memory can be the `M25P128`_ or the `MT25QL128`_. It is
used to store the :doc:`hdl-bootloader`, an application bitstream, and
eventually also user data.
Flash memory organization
-------------------------
The memory contains 16 Megabytes of data, that is 65536 pages of 256 bytes. The
first 6 MiB are used for bitstream storage. The flash format is compatible with
the SDB filesystem, with the SDB descriptor table located at offset
``0x600000``. Locations of the bitstreams are fixed to:
=========================== ==============================================
Address Range Description
=========================== ==============================================
``0x00000000 - 0x000FFFFF`` Bitstream (``.bin``) for the System FPGA
``0x00100000 - 0x005FFFFF`` Bitstream (``.bin``) for the Application FPGA
``0x00600000 - 0x00600FFF`` Obsolete (SDB)
``0x00601000 - 0x00ffffff`` Free space, private data storage.
=========================== ==============================================
Accessing the SPI Flash from the Application FPGA
-------------------------------------------------
:doc:`hdl-bootloader` version 3 allows the Application FPGA to access the SPI
interface of the Flash memory. Once the boot process is done, the System FPGA
routes the following AFPGA pins directly to the Flash memory's SPI interface
(Xilinx UCF file syntax).::
NET "flash_sck_o" LOC=AG26;
NET "flash_mosi_o" LOC=AH26;
NET "flash_cs_n_o" LOC=AG27;
NET "flash_miso_i" LOC=AH27;
NET "flash_sck_o" IOSTANDARD = "LVCMOS33";
NET "flash_mosi_o" IOSTANDARD = "LVCMOS33";
NET "flash_cs_n_o" IOSTANDARD = "LVCMOS33";
NET "flash_miso_i" IOSTANDARD = "LVCMOS33";
.. _`M25P128`: http://www.micron.com/parts/nor-flash/serial-nor-flash/m25p128-vme6gb
.. _`MT25QL128`: https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qlhs_l_128_aba_0.pdf
......@@ -12,6 +12,8 @@ The `SVEC project`_ is hosted on the `Open HardWare Repository`_
:maxdepth: 2
:caption: Contents:
hw-spi-flash
hdl-bootloader
hdl-svec-base
sw-driver
......
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0
memory-map:
name: sxldr
description: SVEC FPGA loader
comment: A very simple serial firmware loader for Xilinx FPGAs. Programs the FPGA using serial slave mode method
bus: wb-32-be
x-wbgen:
hdl_entity: svec_xloader_wb
schema-version:
core: 2.0.0
x-conversions: 1.0.0
x-driver-edge: 1.0.0
x-enums: 1.0.0
x-fesa: 2.0.0
x-gena: 2.0.0
x-hdl: 1.0.0
x-map-info: 1.0.0
x-wbgen: 1.0.0
children:
- reg:
name: CSR
description: Control/status register
width: 32
access: rw
children:
- field:
name: START
description: Start configuration
comment: 'write 1: starts the configuration process.\n write 0: no effect'
range: 0
x-wbgen:
type: MONOSTABLE
- field:
name: DONE
description: Configuration done
comment: 'read 1: the bitstream has been loaded\n read 0: configuration still in progress'
range: 1
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
type: BIT
- field:
name: ERROR
description: Configuration error
comment: 'read 1: an error occured during the configuration (DONE/INIT_B timeout)\n read 0: configuration was successful'
range: 2
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
type: BIT
- field:
name: BUSY
description: Loader busy
comment: 'read 1: the loader is busy (can''t start configuration yet)\n read 0: the loader is ready to re-configure the FPGA'
range: 3
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
type: BIT
- field:
name: MSBF
description: Byte order select
comment: 'write 1: MSB first (big endian host)\n write 0: LSB first (little endian host)'
range: 4
x-wbgen:
access_bus: READ_WRITE
access_dev: READ_ONLY
type: BIT
- field:
name: SWRST
description: Software resest
comment: 'write 1: resets the loader core\n write 0: no effect'
range: 5
x-wbgen:
type: MONOSTABLE
- field:
name: EXIT
description: Exit bootloader mode
comment: 'write 1: terminate bootloader mode and go passive (VME only)'
range: 6
x-wbgen:
type: MONOSTABLE
- field:
name: CLKDIV
description: Serial clock divider
comment: CCLK division ratio. CCLK frequency = F_sysclk / 2 / (CLKDIV + 1)
range: 13-8
x-wbgen:
access_bus: READ_WRITE
access_dev: READ_ONLY
type: SLV
- field:
name: VERSION
description: Bootloader version
range: 21-14
preset: 0x3
x-wbgen:
type: CONSTANT
- reg:
name: BTRIGR
description: Bootloader Trigger Register
width: 32
access: wo
x-hdl:
write-strobe: True
children:
- field:
name: value
description: Trigger Sequence Input
comment: Write a sequence of 0xde, 0xad, 0xbe, 0xef, 0xca, 0xfe, 0xba, 0xbe to enter bootloader mode (VME only)
range: 7-0
x-wbgen:
field_comment: Write a sequence of 0xde, 0xad, 0xbe, 0xef, 0xca, 0xfe, 0xba, 0xbe to enter bootloader mode (VME only)
field_description: Trigger Sequence Input
type: PASS_THROUGH
x-hdl:
type: wire
- reg:
name: FAR
description: Flash Access Register
comment: Provides direct access to the SPI flash memory containing the bitstream.
width: 32
access: rw
x-hdl:
write-strobe: True
children:
- field:
name: DATA
description: SPI Data
comment: Data to be written / read to/from the flash SPI controller.
range: 7-0
x-wbgen:
access_bus: READ_WRITE
access_dev: READ_WRITE
load: LOAD_EXT
type: SLV
- field:
name: XFER
description: SPI Start Transfer
comment: 'write 1: initiate an SPI transfer with an 8-bit data word taken from the <code>DATA</code>field\n write 0: no effect'
range: 8
x-wbgen:
access_bus: READ_WRITE
access_dev: READ_ONLY
type: BIT
- field:
name: READY
description: SPI Ready
comment: 'read 1: Core is ready to initiate another transfer. DATA field contains the data read during previous transaction.\nread 0: core is busy'
range: 9
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
type: BIT
- field:
name: CS
description: SPI Chip Select
comment: 'write 1: Enable target SPI controller\nwrite 0: Disable target SPI controller'
range: 10
x-wbgen:
access_bus: READ_WRITE
access_dev: READ_ONLY
type: BIT
- reg:
name: IDR
description: ID Register
comment: User-defined identification code (g_idr_value generic)
width: 32
access: ro
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
field_comment: User-defined identification code (g_idr_value generic)
field_description: Identification code
type: SLV
- block:
name: FIFO
description: Bitstream FIFO
align: False
size: 12
x-wbgen:
depth: 256
direction: BUS_TO_CORE
kind: fifo
wire_empty: True
wire_full: True
children:
- reg:
name: FIFO_r0
description: 'FIFO ''Bitstream FIFO'' data input register 0'
width: 32
access: wo
children:
- field:
name: XSIZE
description: Entry size
comment: Number of bytes to send (0 = 1 byte .. 3 = full 32-bit word)
range: 1-0
x-wbgen:
type: SLV
- field:
name: XLAST
description: Last xfer
comment: 'write 1: indicates the last word to be written to the FPGA'
range: 2
x-wbgen:
type: BIT
- reg:
name: FIFO_r1
description: 'FIFO ''Bitstream FIFO'' data input register 1'
width: 32
access: wo
children:
- field:
name: XDATA
description: Data
comment: Subsequent words of the bitstream
range: 31-0
x-wbgen:
type: SLV
- reg:
name: FIFO_csr
description: 'FIFO ''Bitstream FIFO'' control/status register'
width: 32
access: rw
x-wbgen:
kind: fifocs
children:
- field:
name: full
description: FIFO full flag
comment: '1: FIFO ''Bitstream FIFO'' is full\n0: FIFO is not full'
range: 16
x-wbgen:
kind: full
type: BIT
- field:
name: empty
description: FIFO empty flag
comment: '1: FIFO ''Bitstream FIFO'' is empty\n0: FIFO is not empty'
range: 17
x-wbgen:
kind: empty
type: BIT
- field:
name: clear_bus
description: FIFO clear
comment: 'write 1: clears FIFO ''Bitstream FIFO\nwrite 0: no effect'
range: 18
x-wbgen:
kind: clear_bus
type: BIT
- field:
name: count
description: FIFO counter
comment: 'Number of data records currently being stored in FIFO ''Bitstream FIFO'''
range: 7-0
x-wbgen:
kind: count
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