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S
Simple VME FMC Carrier SVEC
Commit 5a7478bf authored by Tristan Gingold's avatar Tristan Gingold
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vmecore_test: rewire the interrupt line.

parent 14d2cf23
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Showing with 5 additions and 2 deletions
hdl/top/vmecore_test/svec_vmecore_test_top.vhd
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......@@ -7,7 +7,7 @@
-- Author(s) : Tristan Gingold <tristan.gingold@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-09-19
-- Last update: 2020-06-04
-- Last update: 2020-07-01
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the test design .
......@@ -196,6 +196,7 @@ architecture top of svec_vmecore_test_top is
signal clk_20m_vcxo_buf : std_logic;
signal clk_sys : std_logic;
signal local_reset_n : std_logic;
signal int : std_logic;
signal powerup_reset_cnt : unsigned(7 downto 0) := "00000000";
signal powerup_rst_n : std_logic := '0';
......@@ -342,7 +343,8 @@ begin -- architecture top
vme_o.addr_dir => vme_addr_dir_int,
vme_o.addr_oe_n => vme_addr_oe_n_o,
wb_i => master_in,
wb_o => master_out);
wb_o => master_out,
int_i => int);
vme_ga <= vme_gap_i & vme_ga_i;
......@@ -396,5 +398,6 @@ begin -- architecture top
rst_n_i => local_reset_n,
slave_i => master_out,
slave_o => master_in,
int_o => int,
leds_o => svec_led);
end architecture top;
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