Commit 58314b58 authored by Federico Vaga's avatar Federico Vaga

Merge branch 'proposed_master' into develop

parents 7035a37a d8f4adcc
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
url = https://ohwr.org/project/general-cores.git
[submodule "hdl/ip_cores/vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = git://ohwr.org/hdl-core-lib/vme64x-core.git
url = https://ohwr.org/project/vme64x-core.git
modules = { "local" : [ "hdl/rtl" ] }
if action == "synthesis":
modules["local"].append("hdl/syn/common")
Subproject commit e848b421868886e0d539a24c4978e62b0e48f2f2
Subproject commit 5dde6da558083312cfd98d721e14b36a03e2a0bc
Subproject commit b2fc3ce76485404f831d15f7ce31fdde08e234d5
Subproject commit 1204aeca29ec3c72b6fa615976f000c664c7d152
files = [
"svec_template_regs.vhd",
"svec_template_wr.vhd",
]
files = [ "flash_boot.vhd",
"m25p_flash.vhd",
"mini_vme.vhd",
"spi_master.vhd",
"xilinx_loader.vhd",
"sxldr_wbgen2_pkg.vhd",
"svec_xloader_wb.vhd",
......
-----------------------------------------------------------------------------
-- Title : SPI Bus Master
-- Project : Simple VME64x FMC Carrier (SVEC)
-------------------------------------------------------------------------------
-- File : spi_master.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-01-25
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Just a simple SPI master (bus-less).
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011-2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_master is
generic(
-- clock division ratio (SCLK = clk_sys_i / (2 ** g_div_ratio_log2).
g_div_ratio_log2 : integer := 2;
-- number of data bits per transfer
g_num_data_bits : integer := 2);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- state of the Chip select line (1 = CS active). External control
-- allows for multi-transfer commands (SPI master itself does not
-- control the state of spi_cs_n_o)
cs_i : in std_logic;
-- 1: start next transfer (using CPOL, DATA and SEL from the inputs below)
start_i : in std_logic;
-- Clock polarity: 1: slave clocks in the data on rising SCLK edge, 0: ...
-- on falling SCLK edge
cpol_i : in std_logic;
-- TX Data input
data_i : in std_logic_vector(g_num_data_bits - 1 downto 0);
-- 1: data_o contains the result of last read operation. Core is ready to initiate
-- another transfer.
ready_o : out std_logic;
-- data read from selected slave, valid when ready_o == 1.
data_o : out std_logic_vector(g_num_data_bits - 1 downto 0);
-- these are obvious
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end spi_master;
architecture behavioral of spi_master is
signal divider : unsigned(11 downto 0);
signal tick : std_logic;
signal sreg : std_logic_vector(g_num_data_bits-1 downto 0);
signal rx_sreg : std_logic_vector(g_num_data_bits-1 downto 0);
type t_state is (IDLE, TX_CS, TX_DAT1, TX_DAT2, TX_SCK1, TX_SCK2, TX_CS2, TX_GAP);
signal state : t_state;
signal sclk : std_logic;
signal counter : unsigned(4 downto 0);
begin -- rtl
-- Simple clock divder. Produces a 'tick' signal which defines the timing for
-- the main state machine transitions.
p_divide_spi_clock: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
divider <= (others => '0');
else
if(start_i = '1' or tick = '1') then
divider <= (others => '0');
else
divider <= divider + 1;
end if;
end if;
end if;
end process;
tick <= divider(g_div_ratio_log2);
-- Main state machine. Executes SPI transfers
p_main_fsm: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= IDLE;
sclk <= '0';
sreg <= (others => '0');
rx_sreg <= (others => '0');
spi_mosi_o <= '0';
counter <= (others => '0');
else
case state is
-- Waits for start of transfer command
when IDLE =>
sclk <= '0';
counter <= (others => '0');
if(start_i = '1') then
sreg <= data_i;
state <= TX_CS;
spi_mosi_o <= data_i(sreg'high);
end if;
-- Generates a gap between the externally asserted Chip Select and
-- the beginning of data transfer
when TX_CS =>
if tick = '1' then
state <= TX_DAT1;
end if;
-- Outputs subsequent bits to MOSI line.
when TX_DAT1 =>
if(tick = '1') then
spi_mosi_o <= sreg(sreg'high);
sreg <= sreg(sreg'high-1 downto 0) & '0';
state <= TX_SCK1;
end if;
-- Flips the SCLK (active edge)
when TX_SCK1 =>
if(tick = '1') then
sclk <= not sclk;
counter <= counter + 1;
state <= TX_DAT2;
end if;
-- Shifts in bits read from the slave
when TX_DAT2 =>
if(tick = '1') then
rx_sreg <= rx_sreg(rx_sreg'high-1 downto 0) & spi_miso_i;
state <= TX_SCK2;
end if;
-- Flips the SCLK (inactive edge). Checks if all bits have been
-- transferred.
when TX_SCK2 =>
if(tick = '1') then
sclk <= not sclk;
if(counter = g_num_data_bits) then
state <= TX_CS2;
else
state <= TX_DAT1;
end if;
end if;
-- Generates a gap for de-assertoin of CS line
when TX_CS2 =>
if(tick = '1') then
state <= TX_GAP;
data_o <= rx_sreg;
end if;
when TX_GAP =>
if (tick = '1') then
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
ready_o <= '1' when (state = IDLE and start_i = '0') else '0';
-- SCLK polarity control
spi_sclk_o <= sclk xor cpol_i;
spi_cs_n_o <= not cs_i;
end behavioral;
memory-map:
name: svec_template_regs
bus: wb-32-be
size: 0x2000
children:
- submap:
name: metadata
description: a ROM containing the carrier metadata
size: 0x40
interface: sram
- block:
name: csr
description: carrier and fmc status and control
address: 0x40
children:
- reg:
name: app_offset
description: offset to the application metadata
access: ro
width: 32
- reg:
name: resets
description: global and application resets
access: rw
width: 32
children:
- field:
name: global
range: 0
- field:
name: appl
range: 1
- reg:
name: fmc_presence
description: presence lines for the fmcs
access: ro
width: 32
- reg:
name: unused0
description: unused (status of gennum)
access: ro
width: 32
preset: 0
x-hdl:
type: const
- reg:
name: ddr_status
description: status of the ddr controllers
access: ro
width: 32
children:
- field:
description: Set when ddr4 calibration is done.
name: ddr4_calib_done
range: 0
- field:
description: Set when ddr5 calibration is done.
name: ddr5_calib_done
range: 1
- reg:
name: pcb_rev
description: pcb revision
access: ro
width: 32
children:
- field:
name: rev
range: 4-0
- reg:
name: ddr4_addr
description: address of data to read or to write
access: rw
width: 32
x-hdl:
type: wire
write-strobe: True
- reg:
name: ddr4_data
description: data to read or to write in ddr4
access: rw
width: 32
x-hdl:
type: wire
read-strobe: True
write-strobe: True
read-ack: True
write-ack: True
- submap:
name: therm_id
description: Thermometer and unique id
address: 0x70
size: 0x10
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: fmc_i2c
description: i2c controllers to the fmcs
address: 0x80
size: 0x20
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: flash_spi
description: spi controller to the flash
address: 0xa0
size: 0x20
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: vic
description: vector interrupt controller
address: 0x100
size: 0x100
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: buildinfo
description: a ROM containing build information
size: 0x100
interface: sram
- submap:
name: wrc_regs
address: 0x1000
description: white-rabbit core registers
size: 0x1000
interface: wb-32-be
x-hdl:
busgroup: True
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# User should define the variable svec_template_ucf
files = [ "svec_template_common.ucf" ]
ucf_dict = {
'ddr4': "svec_template_ddr4.ucf",
'ddr5': "svec_template_ddr5.ucf",
'wr': "svec_template_wr.ucf",
'led': "svec_template_led.ucf",
'gpio': "svec_template_gpio.ucf",
}
for p in svec_template_ucf:
f = ucf_dict.get(p, None)
assert f is not None, "unknown name {} in 'svec_template_ucf'".format(p)
if p == 'ddr4' or p == 'ddr5':
files.append('svec_template_ddr_common.ucf')
files.append(f)
#===============================================================================
# IO Constraints
#===============================================================================
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" LOC = R1;
NET "vme_sysreset_n_i" LOC = P4;
NET "vme_retry_oe_o" LOC = R4;
NET "vme_retry_n_o" LOC = AB2;
NET "vme_lword_n_b" LOC = M7;
NET "vme_iackout_n_o" LOC = N3;
NET "vme_iackin_n_i" LOC = P7;
NET "vme_iack_n_i" LOC = N1;
NET "vme_dtack_oe_o" LOC = T1;
NET "vme_dtack_n_o" LOC = R5;
NET "vme_ds_n_i[1]" LOC = Y6;
NET "vme_ds_n_i[0]" LOC = Y7;
NET "vme_data_oe_n_o" LOC = P1;
NET "vme_data_dir_o" LOC = P2;
NET "vme_berr_o" LOC = R3;
NET "vme_as_n_i" LOC = P6;
NET "vme_addr_oe_n_o" LOC = N4;
NET "vme_addr_dir_o" LOC = N5;
NET "vme_irq_o[7]" LOC = R7;
NET "vme_irq_o[6]" LOC = AH2;
NET "vme_irq_o[5]" LOC = AF2;
NET "vme_irq_o[4]" LOC = N9;
NET "vme_irq_o[3]" LOC = N10;
NET "vme_irq_o[2]" LOC = AH4;
NET "vme_irq_o[1]" LOC = AG4;
NET "vme_gap_i" LOC = M6;
NET "vme_ga_i[4]" LOC = V9;
NET "vme_ga_i[3]" LOC = V10;
NET "vme_ga_i[2]" LOC = AJ1;
NET "vme_ga_i[1]" LOC = AH1;
NET "vme_ga_i[0]" LOC = V7;
NET "vme_data_b[31]" LOC = AK3;
NET "vme_data_b[30]" LOC = AH3;
NET "vme_data_b[29]" LOC = T8;
NET "vme_data_b[28]" LOC = T9;
NET "vme_data_b[27]" LOC = AK4;
NET "vme_data_b[26]" LOC = AJ4;
NET "vme_data_b[25]" LOC = W6;
NET "vme_data_b[24]" LOC = W7;
NET "vme_data_b[23]" LOC = AB6;
NET "vme_data_b[22]" LOC = AB7;
NET "vme_data_b[21]" LOC = W9;
NET "vme_data_b[20]" LOC = W10;
NET "vme_data_b[19]" LOC = AK5;
NET "vme_data_b[18]" LOC = AH5;
NET "vme_data_b[17]" LOC = AD6;
NET "vme_data_b[16]" LOC = AC6;
NET "vme_data_b[15]" LOC = AA6;
NET "vme_data_b[14]" LOC = AA7;
NET "vme_data_b[13]" LOC = T6;
NET "vme_data_b[12]" LOC = T7;
NET "vme_data_b[11]" LOC = AG5;
NET "vme_data_b[10]" LOC = AE5;
NET "vme_data_b[9]" LOC = Y11;
NET "vme_data_b[8]" LOC = W11;
NET "vme_data_b[7]" LOC = AF6;
NET "vme_data_b[6]" LOC = AE6;
NET "vme_data_b[5]" LOC = Y8;
NET "vme_data_b[4]" LOC = Y9;
NET "vme_data_b[3]" LOC = AE7;
NET "vme_data_b[2]" LOC = AD7;
NET "vme_data_b[1]" LOC = AA9;
NET "vme_data_b[0]" LOC = AA10;
NET "vme_am_i[5]" LOC = V8;
NET "vme_am_i[4]" LOC = AG3;
NET "vme_am_i[3]" LOC = AF3;
NET "vme_am_i[2]" LOC = AF4;
NET "vme_am_i[1]" LOC = AE4;
NET "vme_am_i[0]" LOC = AK2;
NET "vme_addr_b[31]" LOC = T2;
NET "vme_addr_b[30]" LOC = T3;
NET "vme_addr_b[29]" LOC = T4;
NET "vme_addr_b[28]" LOC = U1;
NET "vme_addr_b[27]" LOC = U3;
NET "vme_addr_b[26]" LOC = U4;
NET "vme_addr_b[25]" LOC = U5;
NET "vme_addr_b[24]" LOC = V1;
NET "vme_addr_b[23]" LOC = V2;
NET "vme_addr_b[22]" LOC = W1;
NET "vme_addr_b[21]" LOC = W3;
NET "vme_addr_b[20]" LOC = AA4;
NET "vme_addr_b[19]" LOC = AA5;
NET "vme_addr_b[18]" LOC = Y1;
NET "vme_addr_b[17]" LOC = Y2;
NET "vme_addr_b[16]" LOC = Y3;
NET "vme_addr_b[15]" LOC = Y4;
NET "vme_addr_b[14]" LOC = AC1;
NET "vme_addr_b[13]" LOC = AC3;
NET "vme_addr_b[12]" LOC = AD1;
NET "vme_addr_b[11]" LOC = AD2;
NET "vme_addr_b[10]" LOC = AB3;
NET "vme_addr_b[9]" LOC = AB4;
NET "vme_addr_b[8]" LOC = AD3;
NET "vme_addr_b[7]" LOC = AD4;
NET "vme_addr_b[6]" LOC = AC4;
NET "vme_addr_b[5]" LOC = AC5;
NET "vme_addr_b[4]" LOC = N7;
NET "vme_addr_b[3]" LOC = N8;
NET "vme_addr_b[2]" LOC = AE1;
NET "vme_addr_b[1]" LOC = AE3;
NET "vme_write_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_sysreset_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_retry_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_retry_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_lword_n_b" IOSTANDARD = "LVCMOS33";
NET "vme_iackout_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_iackin_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_iack_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[*]" IOSTANDARD = "LVCMOS33";
NET "vme_data_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_data_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_berr_o" IOSTANDARD = "LVCMOS33";
NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[*]" IOSTANDARD = "LVCMOS33";
NET "vme_gap_i" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[*]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[*]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[*]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[*]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "rst_n_i" LOC = AD28;
NET "clk_125m_pllref_n_i" LOC = AB30;
NET "clk_125m_pllref_p_i" LOC = AB28;
NET "rst_n_i" IOSTANDARD = "LVCMOS33";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# SPI FLASH
#----------------------------------------
NET "spi_ncs_o" LOC = AG27;
NET "spi_sclk_o" LOC = AG26;
NET "spi_mosi_o" LOC = AH26;
NET "spi_miso_i" LOC = AH27;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS33";
NET "spi_sclk_o" IOSTANDARD = "LVCMOS33";
NET "spi_mosi_o" IOSTANDARD = "LVCMOS33";
NET "spi_miso_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# 1-wire thermometer + unique ID
#----------------------------------------
NET "onewire_b" LOC = AC30;
NET "onewire_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# PCB revision
#----------------------------------------
NET "pcbrev_i[4]" LOC = AF17;
NET "pcbrev_i[3]" LOC = AE17;
NET "pcbrev_i[2]" LOC = AD18;
NET "pcbrev_i[1]" LOC = AE20;
NET "pcbrev_i[0]" LOC = AD20;
NET "pcbrev_i[*]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Carrier I2C EEPROM
#----------------------------------------
NET "carrier_scl_b" LOC = AC29;
NET "carrier_sda_b" LOC = AA30;
NET "carrier_scl_b" IOSTANDARD = "LVCMOS33";
NET "carrier_sda_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# FMC slots management
#----------------------------------------
NET "fmc0_prsnt_m2c_n_i" LOC = N30;
NET "fmc1_prsnt_m2c_n_i" LOC = AE29;
NET "fmc0_scl_b" LOC = P28;
NET "fmc1_scl_b" LOC = W29;
NET "fmc0_sda_b" LOC = P30;
NET "fmc1_sda_b" LOC = V30;
NET "fmc0_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS33";
NET "fmc1_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS33";
NET "fmc0_scl_b" IOSTANDARD = "LVCMOS33";
NET "fmc1_scl_b" IOSTANDARD = "LVCMOS33";
NET "fmc0_sda_b" IOSTANDARD = "LVCMOS33";
NET "fmc1_sda_b" IOSTANDARD = "LVCMOS33";
#===============================================================================
# Timing Constraints
#===============================================================================
#----------------------------------------
# Clocks
#----------------------------------------
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_ref;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_ref;
TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_ref" 8 ns HIGH 50%;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
# Ignore async reset to DDR controller
NET "inst_svec_template/ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# Declaration of domains
NET "inst_svec_template/clk_sys_62m5" TNM_NET = sys_clk;
NET "inst_svec_template/clk_ref_125m" TNM_NET = ref_clk;
TIMEGRP "ref_sync_ffs" = "sync_ffs" EXCEPT "ref_clk";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMESPEC TS_ref_sync_ffs = FROM ref_clk TO "sys_sync_ffs" TIG;
TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
TIMEGRP "ref_sync_reg" = "sync_reg" EXCEPT "ref_clk";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "ref_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg" 16ns DATAPATHONLY;
# DDR0 (bank 4)
NET "ddr4_rzq_b" LOC = L7;
NET "ddr4_we_n_o" LOC = F4;
NET "ddr4_udqs_p_b" LOC = K2;
NET "ddr4_udqs_n_b" LOC = K1;
NET "ddr4_udm_o" LOC = K4;
NET "ddr4_reset_n_o" LOC = G5;
NET "ddr4_ras_n_o" LOC = C1;
NET "ddr4_odt_o" LOC = E4;
NET "ddr4_ldqs_p_b" LOC = J5;
NET "ddr4_ldqs_n_b" LOC = J4;
NET "ddr4_ldm_o" LOC = K3;
NET "ddr4_cke_o" LOC = C4;
NET "ddr4_ck_p_o" LOC = E3;
NET "ddr4_ck_n_o" LOC = E1;
NET "ddr4_cas_n_o" LOC = B1;
NET "ddr4_dq_b[15]" LOC = M1;
NET "ddr4_dq_b[14]" LOC = M2;
NET "ddr4_dq_b[13]" LOC = L1;
NET "ddr4_dq_b[12]" LOC = L3;
NET "ddr4_dq_b[11]" LOC = L4;
NET "ddr4_dq_b[10]" LOC = L5;
NET "ddr4_dq_b[9]" LOC = M3;
NET "ddr4_dq_b[8]" LOC = M4;
NET "ddr4_dq_b[7]" LOC = H1;
NET "ddr4_dq_b[6]" LOC = H2;
NET "ddr4_dq_b[5]" LOC = G1;
NET "ddr4_dq_b[4]" LOC = G3;
NET "ddr4_dq_b[3]" LOC = J1;
NET "ddr4_dq_b[2]" LOC = J3;
NET "ddr4_dq_b[1]" LOC = H3;
NET "ddr4_dq_b[0]" LOC = H4;
NET "ddr4_ba_o[2]" LOC = F3;
NET "ddr4_ba_o[1]" LOC = D1;
NET "ddr4_ba_o[0]" LOC = D2;
NET "ddr4_a_o[13]" LOC = B5;
NET "ddr4_a_o[12]" LOC = A4;
NET "ddr4_a_o[11]" LOC = G4;
NET "ddr4_a_o[10]" LOC = D5;
NET "ddr4_a_o[9]" LOC = A2;
NET "ddr4_a_o[8]" LOC = B2;
NET "ddr4_a_o[7]" LOC = B3;
NET "ddr4_a_o[6]" LOC = F1;
NET "ddr4_a_o[5]" LOC = F2;
NET "ddr4_a_o[4]" LOC = C5;
NET "ddr4_a_o[3]" LOC = E5;
NET "ddr4_a_o[2]" LOC = A3;
NET "ddr4_a_o[1]" LOC = D3;
NET "ddr4_a_o[0]" LOC = D4;
# DDR IO standards and terminations
NET "ddr4_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr4_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr4_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr4_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr4_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr4_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr4_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr4_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr4_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr4_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr4_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr4_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr4_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr4_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr4_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr4_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr4_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr4_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr4_dq_b[*]" IN_TERM = NONE;
NET "ddr4_ldqs_p_b" IN_TERM = NONE;
NET "ddr4_ldqs_n_b" IN_TERM = NONE;
NET "ddr4_udqs_p_b" IN_TERM = NONE;
NET "ddr4_udqs_n_b" IN_TERM = NONE;
# DDR1 (bank 5)
NET "ddr5_rzq_b" LOC = G25;
NET "ddr5_we_n_o" LOC = E26;
NET "ddr5_udqs_p_b" LOC = K28;
NET "ddr5_udqs_n_b" LOC = K30;
NET "ddr5_udm_o" LOC = J27;
NET "ddr5_reset_n_o" LOC = C26;
NET "ddr5_ras_n_o" LOC = K26;
NET "ddr5_odt_o" LOC = E30;
NET "ddr5_ldqs_p_b" LOC = J29;
NET "ddr5_ldqs_n_b" LOC = J30;
NET "ddr5_ldm_o" LOC = J28;
NET "ddr5_cke_o" LOC = B29;
NET "ddr5_ck_p_o" LOC = E27;
NET "ddr5_ck_n_o" LOC = E28;
NET "ddr5_cas_n_o" LOC = K27;
NET "ddr5_dq_b[15]" LOC = M30;
NET "ddr5_dq_b[14]" LOC = M28;
NET "ddr5_dq_b[13]" LOC = M27;
NET "ddr5_dq_b[12]" LOC = M26;
NET "ddr5_dq_b[11]" LOC = L30;
NET "ddr5_dq_b[10]" LOC = L29;
NET "ddr5_dq_b[9]" LOC = L28;
NET "ddr5_dq_b[8]" LOC = L27;
NET "ddr5_dq_b[7]" LOC = F30;
NET "ddr5_dq_b[6]" LOC = F28;
NET "ddr5_dq_b[5]" LOC = G28;
NET "ddr5_dq_b[4]" LOC = G27;
NET "ddr5_dq_b[3]" LOC = G30;
NET "ddr5_dq_b[2]" LOC = G29;
NET "ddr5_dq_b[1]" LOC = H30;
NET "ddr5_dq_b[0]" LOC = H28;
NET "ddr5_ba_o[2]" LOC = D26;
NET "ddr5_ba_o[1]" LOC = C27;
NET "ddr5_ba_o[0]" LOC = D27;
NET "ddr5_a_o[13]" LOC = A28;
NET "ddr5_a_o[12]" LOC = B30;
NET "ddr5_a_o[11]" LOC = A26;
NET "ddr5_a_o[10]" LOC = F26;
NET "ddr5_a_o[9]" LOC = A27;
NET "ddr5_a_o[8]" LOC = B27;
NET "ddr5_a_o[7]" LOC = C29;
NET "ddr5_a_o[6]" LOC = H27;
NET "ddr5_a_o[5]" LOC = H26;
NET "ddr5_a_o[4]" LOC = F27;
NET "ddr5_a_o[3]" LOC = E29;
NET "ddr5_a_o[2]" LOC = C30;
NET "ddr5_a_o[1]" LOC = D30;
NET "ddr5_a_o[0]" LOC = D28;
# DDR IO standards and terminations
NET "ddr5_udqs_p_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_udqs_n_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ldqs_p_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ldqs_n_b[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ck_p_o[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ck_n_o[*]" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_rzq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_we_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_udm_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_reset_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_ras_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_odt_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_ldm_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_cke_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_cas_n_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_dq_b[*]" IN_TERM = NONE;
NET "ddr5_ldqs_p_b[*]" IN_TERM = NONE;
NET "ddr5_ldqs_n_b[*]" IN_TERM = NONE;
NET "ddr5_udqs_p_b[*]" IN_TERM = NONE;
NET "ddr5_udqs_n_b[*]" IN_TERM = NONE;
#----------------------------------------
# Xilinx MCB tweaks
#----------------------------------------
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/c?_pll_lock" TIG;
NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
# Ignore async reset to DDR controller
NET "inst_svec_template/ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "inst_svec_template/clk_ddr_333m" TNM_NET = ddr_clk;
NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
# DDR does not use any sync modules
#TIMEGRP "ddr_sync_ffs" = "sync_ffs" EXCEPT "ddr_clk";
#TIMESPEC TS_ddr_sync_ffs = FROM ddr_clk TO "ddr_sync_ffs" TIG;
#TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
#----------------------------------------
# Front panel IOs
#----------------------------------------
NET "fp_gpio1_b" LOC = T28;
NET "fp_gpio2_b" LOC = R30;
NET "fp_gpio3_b" LOC = V27;
NET "fp_gpio4_b" LOC = U29;
NET "fp_gpio1_a2b_o" LOC = T30;
NET "fp_gpio2_a2b_o" LOC = R29;
NET "fp_gpio34_a2b_o" LOC = V28;
NET "fp_term_en_o[1]" LOC = AB1;
NET "fp_term_en_o[2]" LOC = W5;
NET "fp_term_en_o[3]" LOC = W4;
NET "fp_term_en_o[4]" LOC = V4;
NET "fp_gpio1_b" IOSTANDARD = "LVCMOS33";
NET "fp_gpio2_b" IOSTANDARD = "LVCMOS33";
NET "fp_gpio3_b" IOSTANDARD = "LVCMOS33";
NET "fp_gpio4_b" IOSTANDARD = "LVCMOS33";
NET "fp_gpio1_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio2_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_gpio34_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[*]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Front panel LEDs
#----------------------------------------
NET "fp_led_line_oen_o[0]" LOC = AD26;
NET "fp_led_line_oen_o[1]" LOC = AD27;
NET "fp_led_line_o[0]" LOC = AC27;
NET "fp_led_line_o[1]" LOC = AC28;
NET "fp_led_column_o[0]" LOC = AE30;
NET "fp_led_column_o[1]" LOC = AE27;
NET "fp_led_column_o[2]" LOC = AE28;
NET "fp_led_column_o[3]" LOC = AF28;
NET "fp_led_line_oen_o[*]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[*]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[*]" IOSTANDARD="LVCMOS33";
#===============================================================================
# IO Constraints
#===============================================================================
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "clk_125m_gtp_p_i" LOC = B19;
NET "clk_125m_gtp_n_i" LOC = A19;
NET "clk_20m_vcxo_i" LOC = V26;
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# SFP slot
#----------------------------------------
NET "sfp_txp_o" LOC = B23;
NET "sfp_txn_o" LOC = A23;
NET "sfp_rxp_i" LOC = D22;
NET "sfp_rxn_i" LOC = C22;
NET "sfp_los_i" LOC = W25;
NET "sfp_mod_def0_i" LOC = Y26;
NET "sfp_mod_def1_b" LOC = Y27;
NET "sfp_mod_def2_b" LOC = AA24;
NET "sfp_rate_select_o" LOC = W24;
NET "sfp_tx_disable_o" LOC = AA25;
NET "sfp_tx_fault_i" LOC = AA27;
NET "sfp_los_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS33";
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# DAC interfaces (for VCXO)
#----------------------------------------
NET "pll20dac_din_o" LOC = U28;
NET "pll20dac_sclk_o" LOC = AA28;
NET "pll20dac_sync_n_o" LOC = N28;
NET "pll25dac_din_o" LOC = P25;
NET "pll25dac_sclk_o" LOC = N27;
NET "pll25dac_sync_n_o" LOC = P26;
NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_txd_o" LOC = U27;
NET "uart_rxd_i" LOC = U25;
NET "uart_txd_o" IOSTANDARD = "LVCMOS33";
NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
#===============================================================================
# Timing Constraints
#===============================================================================
#----------------------------------------
# Clocks
#----------------------------------------
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp;
TIMESPEC TS_clk_125m_gtp = PERIOD "clk_125m_gtp" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo";
TIMESPEC TS_clk_20m_vcxo = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%;
NET "inst_svec_template/gen_wr.cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
#-------------------------------------------------------------
# Constrain the phase between input and sampling clock in DMTD
#-------------------------------------------------------------
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1.25 ns DATAPATHONLY;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# Declaration of domains
NET "inst_svec_template/gen_wr.cmp_xwrc_board_svec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "inst_svec_template/gen_wr.cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
# Exceptions for crossings via gc_sync_ffs
TIMEGRP "dmtd_sync_ffs" = "sync_ffs" EXCEPT "clk_dmtd";
TIMEGRP "phy_sync_ffs" = "sync_ffs" EXCEPT "phy_clk";
TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd TO "dmtd_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs = FROM phy_clk TO "phy_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_clk";
TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_project = "svec_golden.xise"
syn_tool = "ise"
syn_top = "svec_golden"
board = "svec"
ctrls = ["bank4_64b_32b"]
svec_template_ucf = ['ddr4']
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/golden",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
This diff is collapsed.
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_project = "svec_golden_wr.xise"
syn_tool = "ise"
syn_top = "svec_golden_wr"
board = "svec"
ctrls = ["bank4_64b_32b"]
svec_template_ucf = ['ddr4', 'wr', 'gpio', 'led']
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/golden_wr",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
......@@ -8,5 +8,6 @@ syn_grade = "-2"
syn_package = "ftg256"
syn_top = "svec_sfpga_top"
syn_project = "svec_sfpga.xise"
syn_tool = "ise"
modules = { "local" : [ "../../top/sfpga_bootloader", "../../platform" ] }
This diff is collapsed.
action = "simulation"
target = "xilinx"
sim_tool = "modelsim"
sim_top = "main"
vcom_opt = "-93 -mixedsvvh"
syn_device = "xc6slx150t"
svec_template_ucf = []
board = "svec"
ctrls = ["bank4_64b_32b"]
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
include_dirs=[fetchto + "/vme64x-core/hdl/sim/vme64x_bfm",
fetchto + "/general-cores/sim"]
files = [ "main.sv", "buildinfo_pkg.vhd" ]
modules = {
"local" : [ "../../rtl" ],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/vme64x-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
`include "vhd_wishbone64_master.svh"
//`include "../regs/golden_regs.vh"
import wishbone_pkg::*;
module main;
reg rst_n = 0;
reg clk_125m_pllref = 0;
wire clk_62m5;
wire rst_62m5_n;
var t_wishbone_master_data64_out ddr4_wb_out =
'{cyc: 1'b0, stb: 1'b0, we: 1'b0, sel: 4'b0, adr: 32'b0, dat: 64'b0};
initial begin
repeat(20) @(posedge clk_125m_pllref);
rst_n = 1;
end
// 125Mhz
always #4ns clk_125m_pllref <= ~clk_125m_pllref;
IVHDWishbone64Master xwb_ddr4(clk_62m5, rst_62m5_n);
IVME64X VME(rst_n);
`DECLARE_VME_BUFFERS(VME.slave);
logic ddr_reset_n;
logic ddr_ck_p;
logic ddr_ck_n;
logic ddr_cke;
logic ddr_ras_n;
logic ddr_cas_n;
logic ddr_we_n;
wire [1:0] ddr_dm;
logic [2:0] ddr_ba;
logic [13:0] ddr_a;
wire [15:0] ddr_dq;
wire [1:0] ddr_dqs_p;
wire [1:0] ddr_dqs_n;
wire ddr_rzq;
logic ddr_odt;
logic [4:0] slot_id = 5'h8;
svec_template_wr
#(.g_with_vic (1'b1),
.g_with_ddr4(1'b1),
.g_SIMULATION(1'b0))
DUT (
.rst_n_i(rst_n),
.clk_125m_pllref_p_i (clk_125m_pllref),
.clk_125m_pllref_n_i (~clk_125m_pllref),
.clk_20m_vcxo_i (1'b0),
.clk_125m_gtp_n_i (1'b0),
.clk_125m_gtp_p_i (1'b1),
.vme_as_n_i (VME_AS_n),
.vme_sysreset_n_i (VME_RST_n),
.vme_write_n_i (VME_WRITE_n),
.vme_am_i (VME_AM),
.vme_ds_n_i (VME_DS_n),
.vme_gap_i (^slot_id),
.vme_ga_i (~slot_id),
.vme_berr_o (VME_BERR),
.vme_dtack_n_o (VME_DTACK_n),
.vme_retry_n_o (VME_RETRY_n),
.vme_retry_oe_o (VME_RETRY_OE),
.vme_lword_n_b (VME_LWORD_n),
.vme_addr_b (VME_ADDR),
.vme_data_b (VME_DATA),
.vme_irq_o (VME_IRQ_n),
.vme_iack_n_i (VME_IACK_n),
.vme_iackin_n_i (VME_IACKIN_n),
.vme_iackout_n_o (VME_IACKOUT_n),
.vme_dtack_oe_o (VME_DTACK_OE),
.vme_data_dir_o (VME_DATA_DIR),
.vme_data_oe_n_o (VME_DATA_OE_N),
.vme_addr_dir_o (VME_ADDR_DIR),
.vme_addr_oe_n_o (VME_ADDR_OE_N),
.fmc0_scl_b (),
.fmc0_sda_b (),
.fmc1_scl_b (),
.fmc1_sda_b (),
.fmc0_prsnt_m2c_n_i (),
.fmc1_prsnt_m2c_n_i (),
.onewire_b (),
.carrier_scl_b (),
.carrier_sda_b (),
.spi_sclk_o (),
.spi_ncs_o (),
.spi_mosi_o (),
.spi_miso_i (),
.uart_rxd_i (),
.uart_txd_o (),
.plldac_sclk_o (),
.plldac_din_o (),
.pll25dac_cs_n_o (),
.pll20dac_cs_n_o (),
.pll20dac_din_o (),
.pll20dac_sclk_o (),
.pll20dac_sync_n_o (),
.pll25dac_din_o (),
.pll25dac_sclk_o (),
.pll25dac_sync_n_o (),
.sfp_txp_o (),
.sfp_txn_o (),
.sfp_rxp_i (),
.sfp_rxn_i (),
.sfp_mod_def0_i (),
.sfp_mod_def1_b (),
.sfp_mod_def2_b (),
.sfp_rate_select_o (),
.sfp_tx_fault_i (),
.sfp_tx_disable_o (),
.sfp_los_i (),
.ddr4_a_o (ddr_a),
.ddr4_ba_o (ddr_ba),
.ddr4_cas_n_o (ddr_cas_n),
.ddr4_ck_p_o (ddr_ck_p),
.ddr4_ck_n_o (ddr_ck_n),
.ddr4_cke_o (ddr_cke),
.ddr4_dq_b (ddr_dq),
.ddr4_ldm_o (ddr_dm[0]),
.ddr4_ldqs_n_b (ddr_dqs_n[0]),
.ddr4_ldqs_p_b (ddr_dqs_p[0]),
.ddr4_odt_o (ddr_odt),
.ddr4_ras_n_o (ddr_ras_n),
.ddr4_reset_n_o (ddr_reset_n),
.ddr4_rzq_b (ddr_rzq),
.ddr4_udm_o (ddr_dm[1]),
.ddr4_udqs_n_b (ddr_dqs_n[1]),
.ddr4_udqs_p_b (ddr_dqs_p[1]),
.ddr4_we_n_o (ddr_we_n),
.ddr5_a_o (),
.ddr5_ba_o (),
.ddr5_cas_n_o (),
.ddr5_ck_p_o (),
.ddr5_ck_n_o (),
.ddr5_cke_o (),
.ddr5_dq_b (),
.ddr5_ldm_o (),
.ddr5_ldqs_n_b (),
.ddr5_ldqs_p_b (),
.ddr5_odt_o (),
.ddr5_ras_n_o (),
.ddr5_reset_n_o (),
.ddr5_rzq_b (),
.ddr5_udm_o (),
.ddr5_udqs_n_b (),
.ddr5_udqs_p_b (),
.ddr5_we_n_o (),
.pcbrev_i (5'h2),
.ddr4_clk_i (clk_62m5),
.ddr4_rst_n_i (rst_62m5_n),
.ddr4_wb_i (xwb_ddr4.out),
.ddr4_wb_o (xwb_ddr4.in),
.ddr5_clk_i (),
.ddr5_rst_n_i (),
.ddr5_wb_i (),
.ddr5_wb_o (),
.ddr4_wr_fifo_empty_o(),
.ddr5_wr_fifo_empty_o(),
.clk_sys_62m5_o (clk_62m5),
.rst_sys_62m5_n_o (rst_62m5_n),
.clk_ref_125m_o (),
.rst_ref_125m_n_o (),
.irq_user_i (),
.wrf_src_o (),
.wrf_src_i (),
.wrf_snk_o (),
.wrf_snk_i (),
.wrs_tx_data_i (),
.wrs_tx_valid_i (),
.wrs_tx_dreq_o (),
.wrs_tx_last_i (),
.wrs_tx_flush_i (),
.wrs_tx_cfg_i (),
.wrs_rx_first_o (),
.wrs_rx_last_o (),
.wrs_rx_data_o (),
.wrs_rx_valid_o (),
.wrs_rx_dreq_i (),
.wrs_rx_cfg_i (),
.wb_eth_master_o (),
.wb_eth_master_i (),
.tm_link_up_o (),
.tm_time_valid_o (),
.tm_tai_o (),
.tm_cycles_o (),
.pps_p_o (),
.pps_led_o (),
.link_ok_o (),
.led_link_o (),
.led_act_o (),
.app_wb_o (),
.app_wb_i ()
);
ddr3
cmp_ddr4 (
.rst_n (ddr_reset_n),
.ck (ddr_ck_p),
.ck_n (ddr_ck_n),
.cke (ddr_cke),
.cs_n (1'b0),
.ras_n (ddr_ras_n),
.cas_n (ddr_cas_n),
.we_n (ddr_we_n),
.dm_tdqs ({ddr_dm[1], ddr_dm[0]}),
.ba (ddr_ba),
.addr (ddr_a),
.dq (ddr_dq),
.dqs ({ddr_dqs_p[1],ddr_dqs_p[0]}),
.dqs_n ({ddr_dqs_n[1],ddr_dqs_n[0]}),
.odt (ddr_odt),
.tdqs_n ()
);
task automatic init_vme64x_core(ref CBusAccessor_VME64x acc);
uint64_t rv;
/* map func0 to 0x80000000, A32 */
acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3);
acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
acc.set_default_modifiers(A32 | D32 | SINGLE);
endtask // init_vme64x_core
initial begin
uint64_t d;
int i, result;
automatic CBusAccessor_VME64x acc = new(VME.tb);
automatic CWishboneAccessor ddr4_acc = xwb_ddr4.get_accessor();
#1us;
init_vme64x_core(acc);
// Display meta data
for (i = 0; i < 8'h20; i += 4)
begin
acc.read('h80000000 | i, d, A32|SINGLE|D32);
$display("Read %x: %x", i, d);
end
acc.read('h80000050, d, A32|SINGLE|D32);
$display("ddr status: %x", d);
// Write ddr4
ddr4_acc.set_mode(PIPELINED);
ddr4_acc.write(0, 64'h1122334455667788, 8);
// Read DDR4
acc.read('h80000000 | 8'h5c, d, A32|SINGLE|D32);
$display("Read data: %08x", d);
acc.read('h80000000 | 8'h58, d, A32|SINGLE|D32);
$display("Read addr: %x", d);
acc.read('h80000000 | 8'h5c, d, A32|SINGLE|D32);
$display("Read data: %08x", d);
acc.read('h80000000 | 8'h58, d, A32|SINGLE|D32);
$display("Read addr: %x", d);
/*
acc.write('h80010000, d, A24|SINGLE|D32);
acc.read('h80010000, d, A24|SINGLE|D32);
acc.write('h80010000 + `ADDR_GLD_I2CR0, ~`GLD_I2CR0_SCL_OUT, A24|SINGLE|D32);
acc.write('h80010000 + `ADDR_GLD_I2CR0, ~`GLD_I2CR0_SDA_OUT, A24|SINGLE|D32);
acc.write('h810000 + `ADDR_GLD_I2CR1, ~`GLD_I2CR0_SCL_OUT, A24|SINGLE|D32);
acc.write('h810000 + `ADDR_GLD_I2CR1, ~`GLD_I2CR0_SDA_OUT, A24|SINGLE|D32);
$display("Read1: %x\n", d);
*/
end
endmodule // main
vsim -quiet -t 10fs -L unisim work.main -novopt
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
log -r /*
run 1us
wave zoomfull
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/vme_write_n_i
add wave -noupdate /main/DUT/vme_sysreset_n_i
add wave -noupdate /main/DUT/vme_retry_oe_o
add wave -noupdate /main/DUT/vme_retry_n_o
add wave -noupdate /main/DUT/vme_lword_n_b
add wave -noupdate /main/DUT/vme_iackout_n_o
add wave -noupdate /main/DUT/vme_iackin_n_i
add wave -noupdate /main/DUT/vme_iack_n_i
add wave -noupdate /main/DUT/vme_gap_i
add wave -noupdate /main/DUT/vme_dtack_oe_o
add wave -noupdate /main/DUT/vme_dtack_n_o
add wave -noupdate /main/DUT/vme_ds_n_i
add wave -noupdate /main/DUT/vme_data_oe_n_o
add wave -noupdate /main/DUT/vme_data_dir_o
add wave -noupdate /main/DUT/vme_berr_o
add wave -noupdate /main/DUT/vme_as_n_i
add wave -noupdate /main/DUT/vme_addr_oe_n_o
add wave -noupdate /main/DUT/vme_addr_dir_o
add wave -noupdate /main/DUT/vme_irq_o
add wave -noupdate /main/DUT/vme_ga_i
add wave -noupdate /main/DUT/vme_data_b
add wave -noupdate /main/DUT/vme_am_i
add wave -noupdate /main/DUT/vme_addr_b
add wave -noupdate -expand /main/DUT/vme_wb_out
add wave -noupdate -expand /main/DUT/vme_wb_in
add wave -noupdate /main/rst_n
add wave -noupdate -divider ddr
add wave -noupdate /main/DUT/ddr4_calib_done
add wave -noupdate /main/DUT/csr_ddr4_addr_out
add wave -noupdate /main/DUT/csr_ddr4_addr_wr
add wave -noupdate /main/DUT/csr_ddr4_addr
add wave -noupdate /main/DUT/csr_ddr4_data_in
add wave -noupdate /main/DUT/csr_ddr4_data_out
add wave -noupdate /main/DUT/csr_ddr4_data_wr
add wave -noupdate /main/DUT/csr_ddr4_data_rd
add wave -noupdate /main/DUT/csr_ddr4_data_wack
add wave -noupdate /main/DUT/csr_ddr4_data_rack
add wave -noupdate /main/DUT/ddr4_read_ip
add wave -noupdate /main/DUT/ddr4_write_ip
add wave -noupdate -expand /main/DUT/ddr4_wb_out
add wave -noupdate /main/DUT/ddr4_wb_in
add wave -noupdate /main/DUT/inst_carrier/rd_int
add wave -noupdate /main/DUT/cmp_vme_core/inst_vme_bus/s_mainFSMstate
add wave -noupdate /main/DUT/cmp_vme_core/inst_vme_bus/s_dataPhase
add wave -noupdate /main/DUT/cmp_vme_core/inst_vme_bus/stall_d
add wave -noupdate /main/DUT/cmp_vme_core/inst_vme_bus/wb_stall_i
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {9332000000 fs} 0}
quietly wave cursor active 1
configure wave -namecolwidth 206
configure wave -valuecolwidth 100
configure wave -justifyvalue right
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {9216871530 fs} {10041217290 fs}
files = [ "svec_top.vhd", "svec_top.ucf", "synthesis_descriptor.vhd" ]
fetchto = "../../ip_cores"
modules = {
"local": [ "../../platform", "../../rtl/golden" ],
"git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git" ]
}
files = ["svec_golden.vhd" ]
modules = {'local': ["../../rtl"]}
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-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SVEC (Simple VME FMC Carrier) SDB descriptor
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2014-02-04
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SVEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "svec-golden ",
syn_commit_id => "daf244bfc22002fbf68514441cd45c23",
syn_tool_name => "ISE ",
syn_tool_version => x"00000133",
syn_date => x"20140204",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "git://ohwr.org/fmc-projects/svec.git "
);
end package synthesis_descriptor;
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files = ["svec_golden_wr.vhd" ]
modules = {'local': ["../../rtl"]}
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