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Simple VME FMC Carrier SVEC
Commit 55dce0b5 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[hdl] fix capitalisation of generics for DDR controller

parent 2ffb0319
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Showing with 5 additions and 4 deletions
CHANGELOG.rst
View file @ 55dce0b5
......@@ -7,6 +7,7 @@ Change Log
Fixed
-----
- [hdl] DDR constraints
- [hdl] DDR controller generic values are now properly capitalised
[1.4.5] 2019-12-16
==================
......
general-cores @ 75d51c0b
Subproject commit 5dde6da558083312cfd98d721e14b36a03e2a0bc
Subproject commit 75d51c0b92015b48b176374f9a387b2d25fa8198
hdl/rtl/svec_base_wr.vhd
View file @ 55dce0b5
......@@ -1052,8 +1052,8 @@ begin -- architecture top
g_RST_ACT_LOW => 0, -- active high reset (simpler internal logic)
g_BANK_PORT_SELECT => "SVEC_BANK4_64B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => boolean'image(g_SIMULATION /= 0),
g_CALIB_SOFT_IP => boolean'image(g_SIMULATION = 0),
g_SIMULATION => to_upper(boolean'image(g_SIMULATION /= 0)),
g_CALIB_SOFT_IP => to_upper(boolean'image(g_SIMULATION = 0)),
g_P0_MASK_SIZE => 8,
g_P0_DATA_PORT_SIZE => 64,
g_P0_BYTE_ADDR_WIDTH => 30,
......
hdl/syn/common/svec_base_ddr_common.ucf
View file @ 55dce0b5
......@@ -7,7 +7,7 @@
NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/c?_pll_lock" TIG;
NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#----------------------------------------
# Asynchronous resets
......
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