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Simple VME FMC Carrier SVEC
Commits
5559e1ec
Commit
5559e1ec
authored
Nov 14, 2019
by
Tristan Gingold
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Import of vmecore_test ad vme16_test.
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Manifest.py
hdl/top/vme16_test/Manifest.py
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svec_vmecore_test_top.ucf
hdl/top/vme16_test/svec_vmecore_test_top.ucf
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svec_vmecore_test_top.vhd
hdl/top/vme16_test/svec_vmecore_test_top.vhd
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vmecore_test.vhd
hdl/top/vme16_test/vmecore_test.vhd
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hdl/top/vme16_test/Manifest.py
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5559e1ec
files
=
[
"svec_vmecore_test_top.vhd"
,
"svec_vmecore_test_top.ucf"
,
"vmecore_test.vhd"
,
]
fetchto
=
"../../ip_cores"
modules
=
{
"git"
:
[
"general-cores"
,
"vme64x-core"
]
}
hdl/top/vme16_test/svec_vmecore_test_top.ucf
0 → 100644
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5559e1ec
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hdl/top/vme16_test/svec_vmecore_test_top.vhd
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5559e1ec
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hdl/top/vme16_test/vmecore_test.vhd
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5559e1ec
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- WB slave test bench for vme64x core
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: vmecore_test
--
-- author: Tristan Gingold <tristan.gingold@cern.ch>
--
-- description:
--
-- WB slave to be synthetized to test features of the vme64x core.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
wishbone_pkg
.
all
;
entity
vmecore_test
is
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
;
int_o
:
out
std_logic
;
leds_o
:
out
std_logic_vector
(
15
downto
0
));
end
vmecore_test
;
architecture
rtl
of
vmecore_test
is
-- Memory map (WB addresses, multiply by 4 to get VME addresses):
-- 0 - 0x1ff: sram (512*4B)
-- 0x1000: leds (4B)
-- 0x1001: last WB transaction (see the code for the format)
-- 0x1002: nbr of WB read accesses (write to clear)
-- 0x1003: nbr of WB write accesses (likewise)
-- 0x1004: nbr of write errors in pattern ram
-- 0x1005: generates bus error.
-- 0x2000: counter (4B). Generate an interrupt when 0 is reached.
-- 0x3000: pattern ram (0x1000 * 4B)
-- 0x4000 - 0x3ff000: pattern ram
signal
counter
:
unsigned
(
31
downto
0
);
signal
leds
:
std_logic_vector
(
15
downto
0
);
signal
last_trans
:
std_logic_vector
(
28
downto
0
);
signal
nbr_read
:
unsigned
(
15
downto
0
);
signal
nbr_write
:
unsigned
(
15
downto
0
);
signal
nbr_write_errors
:
unsigned
(
31
downto
0
);
signal
pattern
:
std_logic_vector
(
31
downto
0
);
type
sram_type
is
array
(
0
to
16
#
1
ff
#
)
of
std_logic_vector
(
31
downto
0
);
signal
sram
:
sram_type
;
begin
-- Pattern of the pattern ram.
pattern
(
31
downto
16
)
<=
not
slave_i
.
adr
(
15
downto
0
);
pattern
(
15
downto
0
)
<=
slave_i
.
adr
(
15
downto
0
);
process
(
clk_sys_i
)
procedure
pattern_write
is
variable
err
:
boolean
;
begin
err
:
=
false
;
for
i
in
3
downto
0
loop
if
slave_i
.
sel
(
i
)
=
'1'
and
(
slave_i
.
dat
(
8
*
i
+
7
downto
8
*
i
)
/=
pattern
(
8
*
i
+
7
downto
8
*
i
))
then
err
:
=
true
;
end
if
;
end
loop
;
if
err
then
nbr_write_errors
<=
nbr_write_errors
+
1
;
end
if
;
end
pattern_write
;
variable
idx
:
natural
;
begin
if
rising_edge
(
clk_sys_i
)
then
slave_o
.
ack
<=
'0'
;
slave_o
.
err
<=
'0'
;
if
rst_n_i
=
'0'
then
counter
<=
(
others
=>
'0'
);
leds
<=
(
others
=>
'0'
);
nbr_read
<=
(
others
=>
'0'
);
nbr_write
<=
(
others
=>
'0'
);
nbr_write_errors
<=
(
others
=>
'0'
);
else
-- Decrementer
if
counter
/=
(
counter
'range
=>
'0'
)
then
counter
<=
counter
-
1
;
end
if
;
if
slave_i
.
stb
=
'1'
and
slave_i
.
cyc
=
'1'
then
if
slave_i
.
adr
(
13
downto
12
)
=
"00"
then
-- Save transaction (very cheap scope).
last_trans
(
23
downto
0
)
<=
slave_i
.
adr
(
23
downto
0
);
last_trans
(
27
downto
24
)
<=
slave_i
.
sel
;
last_trans
(
28
)
<=
slave_i
.
we
;
end
if
;
if
slave_i
.
we
=
'1'
then
-- Write
nbr_write
<=
nbr_write
+
1
;
if
slave_i
.
adr
(
25
downto
14
)
=
x"000"
then
case
slave_i
.
adr
(
13
downto
12
)
is
when
"00"
=>
idx
:
=
to_integer
(
unsigned
(
slave_i
.
adr
(
8
downto
0
)));
for
i
in
3
downto
0
loop
if
slave_i
.
sel
(
i
)
=
'1'
then
sram
(
idx
)(
8
*
i
+
7
downto
8
*
i
)
<=
slave_i
.
dat
(
8
*
i
+
7
downto
8
*
i
);
end
if
;
end
loop
;
when
"01"
=>
case
slave_i
.
adr
(
2
downto
0
)
is
when
"000"
=>
for
i
in
1
downto
0
loop
if
slave_i
.
sel
(
i
)
=
'1'
then
leds
(
8
*
i
+
7
downto
8
*
i
)
<=
slave_i
.
dat
(
8
*
i
+
7
downto
8
*
i
);
end
if
;
end
loop
;
when
"001"
=>
null
;
when
"010"
=>
nbr_read
<=
(
others
=>
'0'
);
when
"011"
=>
nbr_write
<=
(
others
=>
'0'
);
when
"100"
=>
nbr_write_errors
<=
(
others
=>
'0'
);
when
"101"
=>
slave_o
.
err
<=
'1'
;
when
others
=>
null
;
end
case
;
when
"10"
=>
for
i
in
3
downto
0
loop
if
slave_i
.
sel
(
i
)
=
'1'
then
counter
(
8
*
i
+
7
downto
8
*
i
)
<=
unsigned
(
slave_i
.
dat
(
8
*
i
+
7
downto
8
*
i
));
end
if
;
end
loop
;
when
"11"
=>
pattern_write
;
when
others
=>
null
;
end
case
;
else
pattern_write
;
end
if
;
slave_o
.
ack
<=
'1'
;
else
-- Read
nbr_read
<=
nbr_read
+
1
;
if
slave_i
.
adr
(
25
downto
14
)
=
x"000"
then
case
slave_i
.
adr
(
13
downto
12
)
is
when
"00"
=>
idx
:
=
to_integer
(
unsigned
(
slave_i
.
adr
(
8
downto
0
)));
slave_o
.
dat
<=
sram
(
idx
);
when
"01"
=>
case
slave_i
.
adr
(
2
downto
0
)
is
when
"000"
=>
slave_o
.
dat
(
31
downto
16
)
<=
(
others
=>
'0'
);
slave_o
.
dat
(
15
downto
0
)
<=
leds
;
when
"001"
=>
slave_o
.
dat
<=
(
31
downto
29
=>
'0'
)
&
last_trans
;
when
"010"
=>
slave_o
.
dat
(
31
downto
16
)
<=
(
others
=>
'0'
);
slave_o
.
dat
(
15
downto
0
)
<=
std_logic_vector
(
nbr_read
);
when
"011"
=>
slave_o
.
dat
(
31
downto
16
)
<=
(
others
=>
'0'
);
slave_o
.
dat
(
15
downto
0
)
<=
std_logic_vector
(
nbr_write
);
when
"100"
=>
slave_o
.
dat
<=
std_logic_vector
(
nbr_write_errors
);
when
"101"
=>
slave_o
.
err
<=
'1'
;
when
others
=>
null
;
end
case
;
when
"10"
=>
slave_o
.
dat
<=
std_logic_vector
(
counter
);
when
"11"
=>
slave_o
.
dat
<=
pattern
;
when
others
=>
null
;
end
case
;
else
slave_o
.
dat
<=
pattern
;
end
if
;
slave_o
.
ack
<=
'1'
;
end
if
;
end
if
;
end
if
;
end
if
;
end
process
;
leds_o
<=
leds
;
int_o
<=
'1'
when
counter
=
1
else
'0'
;
-- drive unused WB slave_o outputs
slave_o
.
stall
<=
'0'
;
slave_o
.
rty
<=
'0'
;
end
rtl
;
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