Commit 54618b72 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

svec7: updated constraint files with pin assignment

parent add3785a
##################################################################################################
##
## Xilinx, Inc. 2010 www.xilinx.com
## Wed Dec 11 19:18:42 2019
## Tue Sep 22 00:00:43 2020
## Generated by MIG Version 4.1
##
##################################################################################################
......@@ -11,607 +11,47 @@
## FPGA Part: XC7K160T-FBG676
## Speedgrade: -2
## Design Entry: VERILOG
## Frequency: 533.333 MHz
## Frequency: 0 MHz
## Time Period: 1875 ps
##################################################################################################
##################################################################################################
## Controller 0
## Memory Device: DDR3_SDRAM->SODIMMs->svec-custom3
## Memory Device: DDR3_SDRAM->SODIMMs->MT8KTF51264HZ-1G6
## Data Width: 64
## Time Period: 1875
## Data Mask: 1
##################################################################################################
set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_n[*]} ]
set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_p[*]} ]
#create_clock -period 5 [get_ports sys_clk_i]
#create_clock -period 5 [get_ports clk_ref_i]
############## NET - IOSTANDARD ##################
# PadFunction: IO_L1N_T0_34
set_property SLEW FAST [get_ports {ddr3_dq[0]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[0]}]
set_property PACKAGE_PIN U5 [get_ports {ddr3_dq[0]}]
# PadFunction: IO_L2P_T0_34
set_property SLEW FAST [get_ports {ddr3_dq[1]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[1]}]
set_property PACKAGE_PIN U2 [get_ports {ddr3_dq[1]}]
# PadFunction: IO_L2N_T0_34
set_property SLEW FAST [get_ports {ddr3_dq[2]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[2]}]
set_property PACKAGE_PIN U1 [get_ports {ddr3_dq[2]}]
# PadFunction: IO_L4P_T0_34
set_property SLEW FAST [get_ports {ddr3_dq[3]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[3]}]
set_property PACKAGE_PIN V3 [get_ports {ddr3_dq[3]}]
# PadFunction: IO_L4N_T0_34
set_property SLEW FAST [get_ports {ddr3_dq[4]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[4]}]
set_property PACKAGE_PIN W3 [get_ports {ddr3_dq[4]}]
# PadFunction: IO_L5P_T0_34
set_property SLEW FAST [get_ports {ddr3_dq[5]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[5]}]
set_property PACKAGE_PIN U7 [get_ports {ddr3_dq[5]}]
# PadFunction: IO_L5N_T0_34
set_property SLEW FAST [get_ports {ddr3_dq[6]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[6]}]
set_property PACKAGE_PIN V6 [get_ports {ddr3_dq[6]}]
# PadFunction: IO_L6P_T0_34
set_property SLEW FAST [get_ports {ddr3_dq[7]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[7]}]
set_property PACKAGE_PIN V4 [get_ports {ddr3_dq[7]}]
# PadFunction: IO_L7N_T1_34
set_property SLEW FAST [get_ports {ddr3_dq[8]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[8]}]
set_property PACKAGE_PIN Y2 [get_ports {ddr3_dq[8]}]
# PadFunction: IO_L8P_T1_34
set_property SLEW FAST [get_ports {ddr3_dq[9]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[9]}]
set_property PACKAGE_PIN V2 [get_ports {ddr3_dq[9]}]
# PadFunction: IO_L8N_T1_34
set_property SLEW FAST [get_ports {ddr3_dq[10]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[10]}]
set_property PACKAGE_PIN V1 [get_ports {ddr3_dq[10]}]
# PadFunction: IO_L10P_T1_34
set_property SLEW FAST [get_ports {ddr3_dq[11]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[11]}]
set_property PACKAGE_PIN W1 [get_ports {ddr3_dq[11]}]
# PadFunction: IO_L10N_T1_34
set_property SLEW FAST [get_ports {ddr3_dq[12]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[12]}]
set_property PACKAGE_PIN Y1 [get_ports {ddr3_dq[12]}]
# PadFunction: IO_L11P_T1_SRCC_34
set_property SLEW FAST [get_ports {ddr3_dq[13]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[13]}]
set_property PACKAGE_PIN AB2 [get_ports {ddr3_dq[13]}]
# PadFunction: IO_L11N_T1_SRCC_34
set_property SLEW FAST [get_ports {ddr3_dq[14]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[14]}]
set_property PACKAGE_PIN AC2 [get_ports {ddr3_dq[14]}]
# PadFunction: IO_L12P_T1_MRCC_34
set_property SLEW FAST [get_ports {ddr3_dq[15]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[15]}]
set_property PACKAGE_PIN AA3 [get_ports {ddr3_dq[15]}]
# PadFunction: IO_L13P_T2_MRCC_34
set_property SLEW FAST [get_ports {ddr3_dq[16]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[16]}]
set_property PACKAGE_PIN AA4 [get_ports {ddr3_dq[16]}]
# PadFunction: IO_L13N_T2_MRCC_34
set_property SLEW FAST [get_ports {ddr3_dq[17]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[17]}]
set_property PACKAGE_PIN AB4 [get_ports {ddr3_dq[17]}]
# PadFunction: IO_L14P_T2_SRCC_34
set_property SLEW FAST [get_ports {ddr3_dq[18]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[18]}]
set_property PACKAGE_PIN AC4 [get_ports {ddr3_dq[18]}]
# PadFunction: IO_L14N_T2_SRCC_34
set_property SLEW FAST [get_ports {ddr3_dq[19]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[19]}]
set_property PACKAGE_PIN AC3 [get_ports {ddr3_dq[19]}]
# PadFunction: IO_L16N_T2_34
set_property SLEW FAST [get_ports {ddr3_dq[20]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[20]}]
set_property PACKAGE_PIN AC6 [get_ports {ddr3_dq[20]}]
# PadFunction: IO_L17P_T2_34
set_property SLEW FAST [get_ports {ddr3_dq[21]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[21]}]
set_property PACKAGE_PIN Y6 [get_ports {ddr3_dq[21]}]
# PadFunction: IO_L17N_T2_34
set_property SLEW FAST [get_ports {ddr3_dq[22]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[22]}]
set_property PACKAGE_PIN Y5 [get_ports {ddr3_dq[22]}]
# PadFunction: IO_L18P_T2_34
set_property SLEW FAST [get_ports {ddr3_dq[23]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[23]}]
set_property PACKAGE_PIN AD6 [get_ports {ddr3_dq[23]}]
# PadFunction: IO_L20P_T3_34
set_property SLEW FAST [get_ports {ddr3_dq[24]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[24]}]
set_property PACKAGE_PIN AD1 [get_ports {ddr3_dq[24]}]
# PadFunction: IO_L20N_T3_34
set_property SLEW FAST [get_ports {ddr3_dq[25]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[25]}]
set_property PACKAGE_PIN AE1 [get_ports {ddr3_dq[25]}]
# PadFunction: IO_L22P_T3_34
set_property SLEW FAST [get_ports {ddr3_dq[26]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[26]}]
set_property PACKAGE_PIN AE3 [get_ports {ddr3_dq[26]}]
# PadFunction: IO_L22N_T3_34
set_property SLEW FAST [get_ports {ddr3_dq[27]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[27]}]
set_property PACKAGE_PIN AE2 [get_ports {ddr3_dq[27]}]
# PadFunction: IO_L23P_T3_34
set_property SLEW FAST [get_ports {ddr3_dq[28]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[28]}]
set_property PACKAGE_PIN AE6 [get_ports {ddr3_dq[28]}]
# PadFunction: IO_L23N_T3_34
set_property SLEW FAST [get_ports {ddr3_dq[29]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[29]}]
set_property PACKAGE_PIN AE5 [get_ports {ddr3_dq[29]}]
# PadFunction: IO_L24P_T3_34
set_property SLEW FAST [get_ports {ddr3_dq[30]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[30]}]
set_property PACKAGE_PIN AF3 [get_ports {ddr3_dq[30]}]
# PadFunction: IO_L24N_T3_34
set_property SLEW FAST [get_ports {ddr3_dq[31]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[31]}]
set_property PACKAGE_PIN AF2 [get_ports {ddr3_dq[31]}]
# PadFunction: IO_L1N_T0_32
set_property SLEW FAST [get_ports {ddr3_dq[32]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[32]}]
set_property PACKAGE_PIN AF17 [get_ports {ddr3_dq[32]}]
# PadFunction: IO_L2P_T0_32
set_property SLEW FAST [get_ports {ddr3_dq[33]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[33]}]
set_property PACKAGE_PIN AF14 [get_ports {ddr3_dq[33]}]
# PadFunction: IO_L2N_T0_32
set_property SLEW FAST [get_ports {ddr3_dq[34]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[34]}]
set_property PACKAGE_PIN AF15 [get_ports {ddr3_dq[34]}]
# PadFunction: IO_L4P_T0_32
set_property SLEW FAST [get_ports {ddr3_dq[35]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[35]}]
set_property PACKAGE_PIN AD15 [get_ports {ddr3_dq[35]}]
# PadFunction: IO_L4N_T0_32
set_property SLEW FAST [get_ports {ddr3_dq[36]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[36]}]
set_property PACKAGE_PIN AE15 [get_ports {ddr3_dq[36]}]
# PadFunction: IO_L5P_T0_32
set_property SLEW FAST [get_ports {ddr3_dq[37]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[37]}]
set_property PACKAGE_PIN AF19 [get_ports {ddr3_dq[37]}]
# PadFunction: IO_L5N_T0_32
set_property SLEW FAST [get_ports {ddr3_dq[38]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[38]}]
set_property PACKAGE_PIN AF20 [get_ports {ddr3_dq[38]}]
# PadFunction: IO_L6P_T0_32
set_property SLEW FAST [get_ports {ddr3_dq[39]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[39]}]
set_property PACKAGE_PIN AD16 [get_ports {ddr3_dq[39]}]
# PadFunction: IO_L7N_T1_32
set_property SLEW FAST [get_ports {ddr3_dq[40]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[40]}]
set_property PACKAGE_PIN AA15 [get_ports {ddr3_dq[40]}]
# PadFunction: IO_L8P_T1_32
set_property SLEW FAST [get_ports {ddr3_dq[41]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[41]}]
set_property PACKAGE_PIN AC14 [get_ports {ddr3_dq[41]}]
# PadFunction: IO_L8N_T1_32
set_property SLEW FAST [get_ports {ddr3_dq[42]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[42]}]
set_property PACKAGE_PIN AD14 [get_ports {ddr3_dq[42]}]
# PadFunction: IO_L10P_T1_32
set_property SLEW FAST [get_ports {ddr3_dq[43]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[43]}]
set_property PACKAGE_PIN AB14 [get_ports {ddr3_dq[43]}]
# PadFunction: IO_L10N_T1_32
set_property SLEW FAST [get_ports {ddr3_dq[44]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[44]}]
set_property PACKAGE_PIN AB15 [get_ports {ddr3_dq[44]}]
# PadFunction: IO_L11P_T1_SRCC_32
set_property SLEW FAST [get_ports {ddr3_dq[45]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[45]}]
set_property PACKAGE_PIN AA17 [get_ports {ddr3_dq[45]}]
# PadFunction: IO_L11N_T1_SRCC_32
set_property SLEW FAST [get_ports {ddr3_dq[46]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[46]}]
set_property PACKAGE_PIN AA18 [get_ports {ddr3_dq[46]}]
# PadFunction: IO_L12P_T1_MRCC_32
set_property SLEW FAST [get_ports {ddr3_dq[47]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[47]}]
set_property PACKAGE_PIN AB16 [get_ports {ddr3_dq[47]}]
# PadFunction: IO_L13P_T2_MRCC_32
set_property SLEW FAST [get_ports {ddr3_dq[48]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[48]}]
set_property PACKAGE_PIN AC18 [get_ports {ddr3_dq[48]}]
# PadFunction: IO_L13N_T2_MRCC_32
set_property SLEW FAST [get_ports {ddr3_dq[49]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[49]}]
set_property PACKAGE_PIN AD18 [get_ports {ddr3_dq[49]}]
# PadFunction: IO_L14P_T2_SRCC_32
set_property SLEW FAST [get_ports {ddr3_dq[50]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[50]}]
set_property PACKAGE_PIN AB17 [get_ports {ddr3_dq[50]}]
# PadFunction: IO_L14N_T2_SRCC_32
set_property SLEW FAST [get_ports {ddr3_dq[51]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[51]}]
set_property PACKAGE_PIN AC17 [get_ports {ddr3_dq[51]}]
# PadFunction: IO_L16N_T2_32
set_property SLEW FAST [get_ports {ddr3_dq[52]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[52]}]
set_property PACKAGE_PIN AA20 [get_ports {ddr3_dq[52]}]
# PadFunction: IO_L17P_T2_32
set_property SLEW FAST [get_ports {ddr3_dq[53]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[53]}]
set_property PACKAGE_PIN AC19 [get_ports {ddr3_dq[53]}]
# PadFunction: IO_L17N_T2_32
set_property SLEW FAST [get_ports {ddr3_dq[54]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[54]}]
set_property PACKAGE_PIN AD19 [get_ports {ddr3_dq[54]}]
# PadFunction: IO_L18P_T2_32
set_property SLEW FAST [get_ports {ddr3_dq[55]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[55]}]
set_property PACKAGE_PIN AB19 [get_ports {ddr3_dq[55]}]
# PadFunction: IO_L20P_T3_32
set_property SLEW FAST [get_ports {ddr3_dq[56]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[56]}]
set_property PACKAGE_PIN V16 [get_ports {ddr3_dq[56]}]
# PadFunction: IO_L20N_T3_32
set_property SLEW FAST [get_ports {ddr3_dq[57]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[57]}]
set_property PACKAGE_PIN V17 [get_ports {ddr3_dq[57]}]
# PadFunction: IO_L22P_T3_32
set_property SLEW FAST [get_ports {ddr3_dq[58]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[58]}]
set_property PACKAGE_PIN W15 [get_ports {ddr3_dq[58]}]
# PadFunction: IO_L22N_T3_32
set_property SLEW FAST [get_ports {ddr3_dq[59]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[59]}]
set_property PACKAGE_PIN W16 [get_ports {ddr3_dq[59]}]
# PadFunction: IO_L23P_T3_32
set_property SLEW FAST [get_ports {ddr3_dq[60]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[60]}]
set_property PACKAGE_PIN V18 [get_ports {ddr3_dq[60]}]
# PadFunction: IO_L23N_T3_32
set_property SLEW FAST [get_ports {ddr3_dq[61]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[61]}]
set_property PACKAGE_PIN V19 [get_ports {ddr3_dq[61]}]
# PadFunction: IO_L24P_T3_32
set_property SLEW FAST [get_ports {ddr3_dq[62]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[62]}]
set_property PACKAGE_PIN V14 [get_ports {ddr3_dq[62]}]
# PadFunction: IO_L24N_T3_32
set_property SLEW FAST [get_ports {ddr3_dq[63]}]
set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddr3_dq[63]}]
set_property PACKAGE_PIN W14 [get_ports {ddr3_dq[63]}]
# PadFunction: IO_L14P_T2_SRCC_33
set_property SLEW FAST [get_ports {ddr3_addr[15]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[15]}]
set_property PACKAGE_PIN AA10 [get_ports {ddr3_addr[15]}]
# PadFunction: IO_L13N_T2_MRCC_33
set_property SLEW FAST [get_ports {ddr3_addr[14]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]
set_property PACKAGE_PIN AC11 [get_ports {ddr3_addr[14]}]
# PadFunction: IO_L1P_T0_33
set_property SLEW FAST [get_ports {ddr3_addr[13]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]
set_property PACKAGE_PIN V11 [get_ports {ddr3_addr[13]}]
# PadFunction: IO_L1N_T0_33
set_property SLEW FAST [get_ports {ddr3_addr[12]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]
set_property PACKAGE_PIN W11 [get_ports {ddr3_addr[12]}]
# PadFunction: IO_L2P_T0_33
set_property SLEW FAST [get_ports {ddr3_addr[11]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]
set_property PACKAGE_PIN V8 [get_ports {ddr3_addr[11]}]
# PadFunction: IO_L2N_T0_33
set_property SLEW FAST [get_ports {ddr3_addr[10]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]
set_property PACKAGE_PIN V7 [get_ports {ddr3_addr[10]}]
# PadFunction: IO_L4P_T0_33
set_property SLEW FAST [get_ports {ddr3_addr[9]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]
set_property PACKAGE_PIN Y8 [get_ports {ddr3_addr[9]}]
# PadFunction: IO_L4N_T0_33
set_property SLEW FAST [get_ports {ddr3_addr[8]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]
set_property PACKAGE_PIN Y7 [get_ports {ddr3_addr[8]}]
# PadFunction: IO_L5P_T0_33
set_property SLEW FAST [get_ports {ddr3_addr[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]
set_property PACKAGE_PIN Y11 [get_ports {ddr3_addr[7]}]
# PadFunction: IO_L5N_T0_33
set_property SLEW FAST [get_ports {ddr3_addr[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]
set_property PACKAGE_PIN Y10 [get_ports {ddr3_addr[6]}]
# PadFunction: IO_L6P_T0_33
set_property SLEW FAST [get_ports {ddr3_addr[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]
set_property PACKAGE_PIN V9 [get_ports {ddr3_addr[5]}]
# PadFunction: IO_L13P_T2_MRCC_33
set_property SLEW FAST [get_ports {ddr3_addr[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]
set_property PACKAGE_PIN AB11 [get_ports {ddr3_addr[4]}]
# PadFunction: IO_L7P_T1_33
set_property SLEW FAST [get_ports {ddr3_addr[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]
set_property PACKAGE_PIN AE7 [get_ports {ddr3_addr[3]}]
# PadFunction: IO_L7N_T1_33
set_property SLEW FAST [get_ports {ddr3_addr[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]
set_property PACKAGE_PIN AF7 [get_ports {ddr3_addr[2]}]
# PadFunction: IO_L8P_T1_33
set_property SLEW FAST [get_ports {ddr3_addr[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]
set_property PACKAGE_PIN AA8 [get_ports {ddr3_addr[1]}]
# PadFunction: IO_L8N_T1_33
set_property SLEW FAST [get_ports {ddr3_addr[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]
set_property PACKAGE_PIN AA7 [get_ports {ddr3_addr[0]}]
# PadFunction: IO_L9P_T1_DQS_33
set_property SLEW FAST [get_ports {ddr3_ba[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]
set_property PACKAGE_PIN AC8 [get_ports {ddr3_ba[2]}]
# PadFunction: IO_L9N_T1_DQS_33
set_property SLEW FAST [get_ports {ddr3_ba[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]
set_property PACKAGE_PIN AD8 [get_ports {ddr3_ba[1]}]
# PadFunction: IO_L10P_T1_33
set_property SLEW FAST [get_ports {ddr3_ba[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]
set_property PACKAGE_PIN AB7 [get_ports {ddr3_ba[0]}]
# PadFunction: IO_L10N_T1_33
set_property SLEW FAST [get_ports {ddr3_ras_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}]
set_property PACKAGE_PIN AC7 [get_ports {ddr3_ras_n}]
# PadFunction: IO_L11P_T1_SRCC_33
set_property SLEW FAST [get_ports {ddr3_cas_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}]
set_property PACKAGE_PIN AA9 [get_ports {ddr3_cas_n}]
# PadFunction: IO_L11N_T1_SRCC_33
set_property SLEW FAST [get_ports {ddr3_we_n}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}]
set_property PACKAGE_PIN AB9 [get_ports {ddr3_we_n}]
# PadFunction: IO_L12N_T1_MRCC_34
set_property SLEW FAST [get_ports {ddr3_reset_n}]
set_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}]
set_property PACKAGE_PIN AA2 [get_ports {ddr3_reset_n}]
# PadFunction: IO_L15P_T2_DQS_33
set_property SLEW FAST [get_ports {ddr3_cke[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}]
set_property PACKAGE_PIN AB12 [get_ports {ddr3_cke[0]}]
# PadFunction: IO_L15N_T2_DQS_33
set_property SLEW FAST [get_ports {ddr3_odt[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}]
set_property PACKAGE_PIN AC12 [get_ports {ddr3_odt[0]}]
# PadFunction: IO_L12P_T1_MRCC_33
set_property SLEW FAST [get_ports {ddr3_cs_n[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n[0]}]
set_property PACKAGE_PIN AC9 [get_ports {ddr3_cs_n[0]}]
# PadFunction: IO_L1P_T0_34
set_property SLEW FAST [get_ports {ddr3_dm[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]
set_property PACKAGE_PIN U6 [get_ports {ddr3_dm[0]}]
# PadFunction: IO_L7P_T1_34
set_property SLEW FAST [get_ports {ddr3_dm[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]
set_property PACKAGE_PIN Y3 [get_ports {ddr3_dm[1]}]
# PadFunction: IO_L16P_T2_34
set_property SLEW FAST [get_ports {ddr3_dm[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}]
set_property PACKAGE_PIN AB6 [get_ports {ddr3_dm[2]}]
# PadFunction: IO_L19P_T3_34
set_property SLEW FAST [get_ports {ddr3_dm[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}]
set_property PACKAGE_PIN AD4 [get_ports {ddr3_dm[3]}]
# PadFunction: IO_L1P_T0_32
set_property SLEW FAST [get_ports {ddr3_dm[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[4]}]
set_property PACKAGE_PIN AE17 [get_ports {ddr3_dm[4]}]
# PadFunction: IO_L7P_T1_32
set_property SLEW FAST [get_ports {ddr3_dm[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[5]}]
set_property PACKAGE_PIN AA14 [get_ports {ddr3_dm[5]}]
# PadFunction: IO_L16P_T2_32
set_property SLEW FAST [get_ports {ddr3_dm[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[6]}]
set_property PACKAGE_PIN AA19 [get_ports {ddr3_dm[6]}]
# PadFunction: IO_L19P_T3_32
set_property SLEW FAST [get_ports {ddr3_dm[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[7]}]
set_property PACKAGE_PIN Y17 [get_ports {ddr3_dm[7]}]
# PadFunction: IO_L3P_T0_DQS_34
set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[0]}]
set_property PACKAGE_PIN W6 [get_ports {ddr3_dqs_p[0]}]
# PadFunction: IO_L3N_T0_DQS_34
set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[0]}]
set_property PACKAGE_PIN W5 [get_ports {ddr3_dqs_n[0]}]
# PadFunction: IO_L9P_T1_DQS_34
set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[1]}]
set_property PACKAGE_PIN AB1 [get_ports {ddr3_dqs_p[1]}]
# PadFunction: IO_L9N_T1_DQS_34
set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[1]}]
set_property PACKAGE_PIN AC1 [get_ports {ddr3_dqs_n[1]}]
# PadFunction: IO_L15P_T2_DQS_34
set_property SLEW FAST [get_ports {ddr3_dqs_p[2]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[2]}]
set_property PACKAGE_PIN AA5 [get_ports {ddr3_dqs_p[2]}]
# PadFunction: IO_L15N_T2_DQS_34
set_property SLEW FAST [get_ports {ddr3_dqs_n[2]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[2]}]
set_property PACKAGE_PIN AB5 [get_ports {ddr3_dqs_n[2]}]
# PadFunction: IO_L21P_T3_DQS_34
set_property SLEW FAST [get_ports {ddr3_dqs_p[3]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[3]}]
set_property PACKAGE_PIN AF5 [get_ports {ddr3_dqs_p[3]}]
# PadFunction: IO_L21N_T3_DQS_34
set_property SLEW FAST [get_ports {ddr3_dqs_n[3]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[3]}]
set_property PACKAGE_PIN AF4 [get_ports {ddr3_dqs_n[3]}]
# PadFunction: IO_L3P_T0_DQS_32
set_property SLEW FAST [get_ports {ddr3_dqs_p[4]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[4]}]
set_property PACKAGE_PIN AE18 [get_ports {ddr3_dqs_p[4]}]
# PadFunction: IO_L3N_T0_DQS_32
set_property SLEW FAST [get_ports {ddr3_dqs_n[4]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[4]}]
set_property PACKAGE_PIN AF18 [get_ports {ddr3_dqs_n[4]}]
# PadFunction: IO_L9P_T1_DQS_32
set_property SLEW FAST [get_ports {ddr3_dqs_p[5]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[5]}]
set_property PACKAGE_PIN Y15 [get_ports {ddr3_dqs_p[5]}]
# PadFunction: IO_L9N_T1_DQS_32
set_property SLEW FAST [get_ports {ddr3_dqs_n[5]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[5]}]
set_property PACKAGE_PIN Y16 [get_ports {ddr3_dqs_n[5]}]
# PadFunction: IO_L15P_T2_DQS_32
set_property SLEW FAST [get_ports {ddr3_dqs_p[6]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[6]}]
set_property PACKAGE_PIN AD20 [get_ports {ddr3_dqs_p[6]}]
set_property PACKAGE_PIN AB1 [get_ports {ddr3_dqs_p[6]}]
# PadFunction: IO_L15N_T2_DQS_32
# PadFunction: IO_L9N_T1_DQS_34
set_property SLEW FAST [get_ports {ddr3_dqs_n[6]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[6]}]
set_property PACKAGE_PIN AE20 [get_ports {ddr3_dqs_n[6]}]
set_property PACKAGE_PIN AC1 [get_ports {ddr3_dqs_n[6]}]
# PadFunction: IO_L21P_T3_DQS_32
# PadFunction: IO_L3P_T0_DQS_34
set_property SLEW FAST [get_ports {ddr3_dqs_p[7]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_p[7]}]
set_property PACKAGE_PIN W18 [get_ports {ddr3_dqs_p[7]}]
set_property PACKAGE_PIN W6 [get_ports {ddr3_dqs_p[7]}]
# PadFunction: IO_L21N_T3_DQS_32
# PadFunction: IO_L3N_T0_DQS_34
set_property SLEW FAST [get_ports {ddr3_dqs_n[7]}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ddr3_dqs_n[7]}]
set_property PACKAGE_PIN W19 [get_ports {ddr3_dqs_n[7]}]
set_property PACKAGE_PIN W5 [get_ports {ddr3_dqs_n[7]}]
# PadFunction: IO_L3P_T0_DQS_33
# PadFunction: IO_L21P_T3_DQS_33
set_property SLEW FAST [get_ports {ddr3_ck_p[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}]
set_property PACKAGE_PIN W10 [get_ports {ddr3_ck_p[0]}]
set_property PACKAGE_PIN AE12 [get_ports {ddr3_ck_p[0]}]
# PadFunction: IO_L3N_T0_DQS_33
# PadFunction: IO_L21N_T3_DQS_33
set_property SLEW FAST [get_ports {ddr3_ck_n[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}]
set_property PACKAGE_PIN W9 [get_ports {ddr3_ck_n[0]}]
set_property PACKAGE_PIN AF12 [get_ports {ddr3_ck_n[0]}]
......@@ -619,9 +59,9 @@ set_property LOC PHASER_OUT_PHY_X1Y3 [get_cells -hier -filter {NAME =~ */ddr_ph
set_property LOC PHASER_OUT_PHY_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]
......@@ -631,9 +71,9 @@ set_property LOC PHASER_IN_PHY_X1Y3 [get_cells -hier -filter {NAME =~ */ddr_phy
set_property LOC PHASER_IN_PHY_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]
set_property LOC PHASER_IN_PHY_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]
set_property LOC PHASER_IN_PHY_X1Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]
## set_property LOC PHASER_IN_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]
## set_property LOC PHASER_IN_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]
## set_property LOC PHASER_IN_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]
## set_property LOC PHASER_IN_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]
set_property LOC PHASER_IN_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]
set_property LOC PHASER_IN_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]
set_property LOC PHASER_IN_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]
......@@ -645,9 +85,9 @@ set_property LOC OUT_FIFO_X1Y3 [get_cells -hier -filter {NAME =~ */ddr_phy_4lan
set_property LOC OUT_FIFO_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]
set_property LOC OUT_FIFO_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]
set_property LOC OUT_FIFO_X1Y0 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]
set_property LOC OUT_FIFO_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]
set_property LOC OUT_FIFO_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]
set_property LOC OUT_FIFO_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]
set_property LOC OUT_FIFO_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]
set_property LOC OUT_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]
set_property LOC OUT_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]
set_property LOC OUT_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]
......@@ -683,13 +123,6 @@ set_property LOC PLLE2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infra
set_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}]
set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
-to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
-setup 6
set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
-to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
-hold 5
set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]]
......
......@@ -7,59 +7,65 @@ set_property IOSTANDARD LVDS_25 [get_ports {clk_125m_pllref_p_i}]
# PadFunction: IO_L13N_T2_MRCC_14
set_property PACKAGE_PIN F23 [get_ports {clk_125m_pllref_n_i}]
set_property IOSTANDARD LVDS_25 [get_ports {clk_125m_pllref_n_i}]
# PadFunction: MGTREFCLK0N_115
set_property PACKAGE_PIN H5 [get_ports {clk_125m_gtx_n_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk_125m_gtx_n_i}]
# PadFunction: MGTREFCLK0P_115
set_property PACKAGE_PIN H6 [get_ports {clk_125m_gtx_p_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk_125m_gtx_p_i}]
# PadFunction: IO_L13P_T2_MRCC_16
set_property PACKAGE_PIN C12 [get_ports {clk_fpga2_p_i}]
set_property IOSTANDARD LVDS_25 [get_ports {clk_fpga2_p_i}]
# PadFunction: IO_L13N_T2_MRCC_16
set_property PACKAGE_PIN C11 [get_ports {clk_fpga2_n_i}]
# PadFunction: MGTREFCLK1N_115
set_property PACKAGE_PIN K5 [get_ports {clk_125m_gtx_115_n_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk_125m_gtx_115_n_i}]
# PadFunction: MGTREFCLK1P_115
set_property PACKAGE_PIN K6 [get_ports {clk_125m_gtx_115_p_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk_125m_gtx_115_p_i}]
# PadFunction: MGTREFCLK1N_116
set_property PACKAGE_PIN F5 [get_ports {clk_125m_gtx_116_n_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk_125m_gtx_116_n_i}]
# PadFunction: MGTREFCLK1P_116
set_property PACKAGE_PIN F6 [get_ports {clk_125m_gtx_116_p_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk_125m_gtx_116_p_i}]
# PadFunction: IO_L13N_T2_MRCC_13
set_property PACKAGE_PIN P21 [get_ports {clk_fpga2_n_i}]
set_property IOSTANDARD LVDS_25 [get_ports {clk_fpga2_n_i}]
# PadFunction: IO_L12P_T1_MRCC_16
set_property PACKAGE_PIN E10 [get_ports {clk_si57x_p_i}]
# PadFunction: IO_L13P_T2_MRCC_13
set_property PACKAGE_PIN R21 [get_ports {clk_fpga2_p_i}]
set_property IOSTANDARD LVDS_25 [get_ports {clk_fpga2_p_i}]
# PadFunction: IO_L12P_T1_MRCC_13
set_property PACKAGE_PIN N21 [get_ports {clk_si57x_p_i}]
set_property IOSTANDARD LVDS_25 [get_ports {clk_si57x_p_i}]
# PadFunction: IO_L12N_T1_MRCC_16
set_property PACKAGE_PIN D10 [get_ports {clk_si57x_n_i}]
# PadFunction: IO_L12N_T1_MRCC_13
set_property PACKAGE_PIN N22 [get_ports {clk_si57x_n_i}]
set_property IOSTANDARD LVDS_25 [get_ports {clk_si57x_n_i}]
# PadFunction: IO_L12P_T1_MRCC_12
set_property PACKAGE_PIN Y23 [get_ports {fmc0_clk_m2c_p_i[0]}]
# PadFunction: IO_L13P_T2_MRCC_12
set_property PACKAGE_PIN Y22 [get_ports {fmc0_clk_m2c_p_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {fmc0_clk_m2c_p_i[0]}]
# PadFunction: IO_L12N_T1_MRCC_12
set_property PACKAGE_PIN AA24 [get_ports {fmc0_clk_m2c_n_i[0]}]
# PadFunction: IO_L13N_T2_MRCC_12
set_property PACKAGE_PIN AA22 [get_ports {fmc0_clk_m2c_n_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {fmc0_clk_m2c_n_i[0]}]
# PadFunction: IO_L13P_T2_MRCC_12
set_property PACKAGE_PIN Y22 [get_ports {fmc0_clk_m2c_p_i[1]}]
# PadFunction: IO_L12P_T1_MRCC_12
set_property PACKAGE_PIN Y23 [get_ports {fmc0_clk_m2c_p_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {fmc0_clk_m2c_p_i[1]}]
# PadFunction: IO_L13N_T2_MRCC_12
set_property PACKAGE_PIN AA22 [get_ports {fmc0_clk_m2c_n_i[1]}]
# PadFunction: IO_L12N_T1_MRCC_12
set_property PACKAGE_PIN AA24 [get_ports {fmc0_clk_m2c_n_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {fmc0_clk_m2c_n_i[1]}]
# PadFunction: IO_L12P_T1_MRCC_13
set_property PACKAGE_PIN N21 [get_ports {fmc1_clk_m2c_p_i[0]}]
# PadFunction: IO_L12P_T1_MRCC_AD5P_15
set_property PACKAGE_PIN F17 [get_ports {fmc1_clk_m2c_p_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {fmc1_clk_m2c_p_i[0]}]
# PadFunction: IO_L12N_T1_MRCC_13
set_property PACKAGE_PIN N22 [get_ports {fmc1_clk_m2c_n_i[0]}]
# PadFunction: IO_L12N_T1_MRCC_AD5N_15
set_property PACKAGE_PIN E17 [get_ports {fmc1_clk_m2c_n_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {fmc1_clk_m2c_n_i[0]}]
# PadFunction: IO_L13P_T2_MRCC_13
set_property PACKAGE_PIN R21 [get_ports {fmc1_clk_m2c_p_i[1]}]
# PadFunction: IO_L13P_T2_MRCC_15
set_property PACKAGE_PIN E18 [get_ports {fmc1_clk_m2c_p_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {fmc1_clk_m2c_p_i[1]}]
# PadFunction: IO_L13P_T2_MRCC_13
set_property PACKAGE_PIN R21 [get_ports {fmc1_clk_m2c_n_i[1]}]
# PadFunction: IO_L13N_T2_MRCC_15
set_property PACKAGE_PIN D18 [get_ports {fmc1_clk_m2c_n_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {fmc1_clk_m2c_n_i[1]}]
# PadFunction: IO_L12P_T1_MRCC_AD5P_15
set_property PACKAGE_PIN F17 [get_ports {fmc0_la_p_b[0]}]
# PadFunction: IO_L12P_T1_MRCC_16
set_property PACKAGE_PIN E10 [get_ports {fmc0_la_p_b[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {fmc0_la_p_b[0]}]
# PadFunction: IO_L12N_T1_MRCC_AD5N_15
set_property PACKAGE_PIN E17 [get_ports {fmc0_la_n_b[0]}]
# PadFunction: IO_L12N_T1_MRCC_16
set_property PACKAGE_PIN D10 [get_ports {fmc0_la_n_b[0]}]