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Simple VME FMC Carrier SVEC
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Simple VME FMC Carrier SVEC
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53203b3c
Commit
53203b3c
authored
Aug 02, 2019
by
Dimitris Lampridis
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[hdl] relax DMTD phase constraint
parent
416aea5d
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svec_template_wr.ucf
hdl/rtl/svec_template_wr.ucf
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hdl/rtl/svec_template_wr.ucf
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53203b3c
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@@ -84,14 +84,15 @@ NET "inst_svec_template/gen_wr.cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spa
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
#----------------------------------------
# WR DMTD tweaks
#----------------------------------------
#-------------------------------------------------------------
# Constrain the phase between input and sampling clock in DMTD
#-------------------------------------------------------------
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1
.25
ns DATAPATHONLY;
#----------------------------------------
# Cross-clock domain sync
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