svec golden: add code to test DMA.

5128aee2 · Tristan Gingold · f2f9dc31 · 5128aee2
Commit 5128aee2 authored Apr 09, 2020 by Tristan Gingold
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svec_golden.vhd hdl/top/golden/svec_golden.vhd +60 -1

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--- a/hdl/top/golden/svec_golden.vhd
+++ b/hdl/top/golden/svec_golden.vhd
@@ -296,5 +296,64 @@ begin
      app_wb_o => app_wb_out,
      app_wb_i => app_wb_in
    );
-  app_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
+  app_wb_in.err <= '0';
+  app_wb_in.rty <= '0';
+  app_wb_in.stall <= '0';
+
+  --  Add a small RAM
+  --  Memory map:
+  --  0x0000 ..  : base
+  --  0x2000     : indirect address
+  --  0x2004     : indirect data
+  --  0x4000 ..  : RAM (8KB)
+  process (clk_sys_62m5) is
+    type t_mem32 is array (natural range <>) of std_logic_vector(31 downto 0);
+    constant c_memsz : natural := 13;
+    variable mem : t_mem32 (2**(c_memsz-2) - 1 downto 0);
+    subtype t_mem_rng is natural range c_memsz - 1 downto 2;
+    variable addr : natural;
+    variable fifo_idx : std_logic_vector(t_mem_rng);
+    variable mem_acc : boolean;
+  begin
+    if rising_edge(clk_sys_62m5) then
+      if rst_n_i = '0' then
+        fifo_idx := (others => '0');
+      elsif app_wb_out.cyc = '1' and app_wb_out.stb = '1' then
+        --  Note: address is passed unmodified, but cyc/stb is never present
+        --  between 0x0000-0x1fff.
+        mem_acc := True;
+        if app_wb_out.adr(c_memsz) = '0' then
+          --  Direct RAM area
+          addr := to_integer (unsigned(app_wb_out.adr (t_mem_rng)));
+        elsif app_wb_out.adr(t_mem_rng) = (t_mem_rng => '0') then
+          --  FIFO addr register
+          mem_acc := False;
+          if app_wb_out.we = '1' then
+            fifo_idx := app_wb_out.dat(t_mem_rng);
+          else
+            app_wb_in.dat <= (others => '0');
+            app_wb_in.dat(t_mem_rng) <= fifo_idx;
+          end if;
+        else
+          --  FIFO data register
+          addr := to_integer (unsigned(fifo_idx));
+          fifo_idx := std_logic_vector (unsigned (fifo_idx) + 1);
+        end if;
+        if mem_acc then
+          if app_wb_out.we = '1' then
+            for i in 3 downto 0 loop
+              if app_wb_out.sel (i) = '1' then
+                mem(addr)(8*i + 7 downto 8*i) := app_wb_out.dat(8*i + 7 downto 8*i);
+              end if;
+            end loop;
+          else
+            app_wb_in.dat <= mem(addr);
+          end if;
+        end if;
+        app_wb_in.ack <= '1';
+      else
+        app_wb_in.ack <= '0';
+      end if;
+    end if;
+  end process;
 end architecture top;