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Simple VME FMC Carrier SVEC
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Simple VME FMC Carrier SVEC
Commits
50ace067
Commit
50ace067
authored
Feb 07, 2014
by
Tomasz Wlostowski
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hdl/rtl/bootloader: re-genrated WB slave using latest wbgen2 (with FIFO CSR.CLEAR bit fix)
parent
e1f52292
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2 changed files
with
8 additions
and
7 deletions
+8
-7
svec_xloader_wb.vhd
hdl/rtl/bootloader/svec_xloader_wb.vhd
+3
-2
sxldr_wbgen2_pkg.vhd
hdl/rtl/bootloader/sxldr_wbgen2_pkg.vhd
+5
-5
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hdl/rtl/bootloader/svec_xloader_wb.vhd
View file @
50ace067
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : svec_xloader_wb.vhd
-- Author : auto-generated by wbgen2 from svec_xloader_wb.wb
-- Created :
Mon Sep 2 10:21:20 2013
-- Created :
Fri Feb 7 11:31:10 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE svec_xloader_wb.wb
...
...
@@ -302,12 +302,13 @@ begin
ack_in_progress
<=
'1'
;
when
"110"
=>
if
(
wb_we_i
=
'1'
)
then
if
(
rd
data_reg
(
18
)
=
'1'
)
then
if
(
wr
data_reg
(
18
)
=
'1'
)
then
sxldr_fifo_clear_bus_int
<=
'1'
;
end
if
;
end
if
;
rddata_reg
(
16
)
<=
sxldr_fifo_full_int
;
rddata_reg
(
17
)
<=
sxldr_fifo_empty_int
;
rddata_reg
(
18
)
<=
'0'
;
rddata_reg
(
7
downto
0
)
<=
sxldr_fifo_usedw_int
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
...
...
hdl/rtl/bootloader/sxldr_wbgen2_pkg.vhd
View file @
50ace067
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : sxldr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from svec_xloader_wb.wb
-- Created :
Mon Sep 2 10:21:20 2013
-- Created :
Fri Feb 7 11:31:10 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE svec_xloader_wb.wb
...
...
@@ -87,11 +87,11 @@ end package;
package
body
sxldr_wbgen2_pkg
is
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
is
begin
if
(
x
=
'X'
or
x
=
'U'
)
then
return
'
0
'
;
if
x
=
'1'
then
return
'
1
'
;
else
return
x
;
end
if
;
return
'0'
;
end
if
;
end
function
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
is
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
...
...
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