update changelog with hdl-related changes

5075aa8e · Dimitris Lampridis · Dimitris Lampridis · 4c6598db · 5075aa8e
Commit 5075aa8e authored Dec 05, 2022 by Dimitris Lampridis Committed by Dimitris Lampridis Dec 05, 2022
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CHANGELOG.rst CHANGELOG.rst +14 -0

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@@ -13,13 +13,27 @@ Added
 - ci: better automation
 - sw: support for Linux 5.10

+Removed
+-------
+- hdl: unused and obsolete top-levels and simulations
+- hdl: Xilinx chipscope for SFPGA (files were actually for AFPGA)
+
 Changed
 -------
+- hdl: 'golden_wr' top-level renamed to 'wr_example'
+- hdl: 'template' testbench now used for simulating the golden top-level
 - sw|API change: the API to flash a bitstream moved from debugfs to sysfs. The
  Linux kernel community removed API we used. The same behavior was achievable
  only using sysfs.
 - bld: improved Makefiles

+Fixed
+-----
+- hdl: building of all top-levels
+- hdl: missing ddr and wr-cores dependencies
+- hdl: corrected and re-enabled timing constraints
+- hdl: location of general-cores in rtl Manifest
+
 2.0.4 - 2021-07-29
 ==================
 Fixed