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Simple VME FMC Carrier SVEC
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Simple VME FMC Carrier SVEC
Commits
47d1cb6d
Commit
47d1cb6d
authored
Feb 23, 2017
by
Tomasz Wlostowski
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bootloader: make sure flash is always visible for the SFPGA
parent
9cd6c291
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11 changed files
with
572 additions
and
502 deletions
+572
-502
flash_boot.vhd
hdl/rtl/bootloader/flash_boot.vhd
+10
-1
sfpga_bootloader.vhd
hdl/rtl/bootloader/sfpga_bootloader.vhd
+6
-2
svec_xloader_wb.vhd
hdl/rtl/bootloader/svec_xloader_wb.vhd
+2
-2
svec_xloader_wb.wb
hdl/rtl/bootloader/svec_xloader_wb.wb
+1
-1
sxldr_wbgen2_pkg.vhd
hdl/rtl/bootloader/sxldr_wbgen2_pkg.vhd
+1
-1
svec_top.xise
hdl/syn/golden/svec_top.xise
+494
-480
svec_sfpga.xise
hdl/syn/sfpga_bootloader/svec_sfpga.xise
+1
-0
svec_top.ucf
hdl/top/golden/svec_top.ucf
+11
-0
svec_top.vhd
hdl/top/golden/svec_top.vhd
+35
-6
synthesis_descriptor.vhd
hdl/top/golden/synthesis_descriptor.vhd
+2
-2
svec_sfpga_top.vhd
hdl/top/sfpga_bootloader/svec_sfpga_top.vhd
+9
-7
No files found.
hdl/rtl/bootloader/flash_boot.vhd
View file @
47d1cb6d
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-01-24
-- Last update: 201
4-01-15
-- Last update: 201
5-11-10
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -77,6 +77,8 @@ entity flash_boot is
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
;
flash_select_o
:
out
std_logic
;
no_bitstream_p1_o
:
out
std_logic
);
...
...
@@ -177,11 +179,15 @@ begin -- rtl
xldr_start_o
<=
'0'
;
xldr_empty_o
<=
'1'
;
no_bitstream_int
<=
'0'
;
flash_select_o
<=
'0'
;
else
case
state
is
-- Wait until we are allowed to start flash boot sequence
when
STARTUP
=>
flash_select_o
<=
'0'
;
if
enable_i
=
'1'
then
flash_select_o
<=
'1'
;
state
<=
SELECT_SDB
;
byte_count
<=
(
others
=>
'0'
);
end
if
;
...
...
@@ -272,6 +278,8 @@ begin -- rtl
when
NO_BITSTREAM
=>
flash_read
<=
'0'
;
no_bitstream_int
<=
'1'
;
flash_select_o
<=
'0'
;
if
enable_i
=
'0'
then
state
<=
STARTUP
;
end
if
;
...
...
@@ -279,6 +287,7 @@ begin -- rtl
-- Bitstream was correctly loaded. Wait forever (or until reset).
when
BOOT_DONE
=>
flash_read
<=
'0'
;
flash_select_o
<=
'0'
;
end
case
;
end
if
;
...
...
hdl/rtl/bootloader/sfpga_bootloader.vhd
View file @
47d1cb6d
...
...
@@ -101,7 +101,9 @@ entity sfpga_bootloader is
spi_cs_n_o
:
out
std_logic
;
spi_sclk_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
spi_miso_i
:
in
std_logic
;
flash_select_o
:
out
std_logic
);
end
sfpga_bootloader
;
...
...
@@ -168,6 +170,7 @@ architecture behavioral of sfpga_bootloader is
spi_sclk_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
;
flash_select_o
:
out
std_logic
;
no_bitstream_p1_o
:
out
std_logic
);
end
component
;
...
...
@@ -270,6 +273,7 @@ begin -- behavioral
spi_sclk_o
=>
spi_sclk_o
,
spi_mosi_o
=>
spi_mosi_o
,
spi_miso_i
=>
spi_miso_i
,
flash_select_o
=>
flash_select_o
,
no_bitstream_p1_o
=>
flash_no_bitstream_p1
);
-- Route host registers to the boot source multiplexer (p_select_boot_source).
...
...
@@ -290,7 +294,7 @@ begin -- behavioral
-- Multiplexes the access to the Xilinx Serial Bootloader module between
-- the host (accessed via Wishbine registers) and the internal Flash loader
p_select_boot_source
:
process
(
from_host_ldr
,
from_flash_ldr
,
from_xilinx_boot
)
p_select_boot_source
:
process
(
boot_source
,
from_host_ldr
,
from_flash_ldr
,
from_xilinx_boot
)
begin
case
boot_source
is
when
FLASH
=>
...
...
hdl/rtl/bootloader/svec_xloader_wb.vhd
View file @
47d1cb6d
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : svec_xloader_wb.vhd
-- Author : auto-generated by wbgen2 from svec_xloader_wb.wb
-- Created :
Mon Aug 11 10:59:42 2014
-- Created :
Tue Nov 10 13:38:15 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE svec_xloader_wb.wb
...
...
@@ -131,7 +131,7 @@ begin
rddata_reg
(
5
)
<=
'0'
;
rddata_reg
(
6
)
<=
'0'
;
rddata_reg
(
13
downto
8
)
<=
sxldr_csr_clkdiv_int
;
rddata_reg
(
21
downto
14
)
<=
"00000
011
"
;
rddata_reg
(
21
downto
14
)
<=
"00000
100
"
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
...
...
hdl/rtl/bootloader/svec_xloader_wb.wb
View file @
47d1cb6d
...
...
@@ -125,7 +125,7 @@ peripheral {
prefix = "VERSION";
type = CONSTANT;
size = 8;
value =
3
;
value =
4
;
}
};
...
...
hdl/rtl/bootloader/sxldr_wbgen2_pkg.vhd
View file @
47d1cb6d
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : sxldr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from svec_xloader_wb.wb
-- Created :
Mon Aug 11 10:59:42 2014
-- Created :
Tue Nov 10 13:38:15 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE svec_xloader_wb.wb
...
...
hdl/syn/golden/svec_top.xise
View file @
47d1cb6d
This source diff could not be displayed because it is too large. You can
view the blob
instead.
hdl/syn/sfpga_bootloader/svec_sfpga.xise
View file @
47d1cb6d
...
...
@@ -216,6 +216,7 @@
<property
xil_pn:name=
"Preferred Language"
xil_pn:value=
"Verilog"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Produce Verbose Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Project Description"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Project Generator"
xil_pn:value=
"ProjNav"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Property Specification in Project File"
xil_pn:value=
"Store all values"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"RAM Extraction"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"RAM Style"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
...
...
hdl/top/golden/svec_top.ucf
View file @
47d1cb6d
...
...
@@ -256,3 +256,14 @@ NET "fmc0_scl_b" IOSTANDARD = "LVCMOS33";
NET "fmc0_sda_b" IOSTANDARD = "LVCMOS33";
NET "flash_sck_o" LOC=AG26;
NET "flash_mosi_o" LOC=AH26;
NET "flash_cs_n_o" LOC=AG27;
NET "flash_miso_i" LOC=AH27;
NET "flash_sck_o" IOSTANDARD = "LVCMOS33";
NET "flash_mosi_o" IOSTANDARD = "LVCMOS33";
NET "flash_cs_n_o" IOSTANDARD = "LVCMOS33";
NET "flash_miso_i" IOSTANDARD = "LVCMOS33";
hdl/top/golden/svec_top.vhd
View file @
47d1cb6d
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2014-0
2-03
-- Last update: 2014-0
8-11
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -104,7 +104,13 @@ entity svec_top is
fmc1_scl_b
:
inout
std_logic
;
fmc1_sda_b
:
inout
std_logic
;
tempid_dq_b
:
inout
std_logic
tempid_dq_b
:
inout
std_logic
;
flash_sck_o
:
out
std_logic
;
flash_mosi_o
:
out
std_logic
;
flash_cs_n_O
:
out
std_logic
;
flash_miso_i
:
in
std_logic
);
end
svec_top
;
...
...
@@ -173,19 +179,21 @@ architecture rtl of svec_top is
signal
VME_ADDR_b_out
:
std_logic_vector
(
31
downto
1
);
signal
VME_LWORD_n_b_out
,
VME_DATA_DIR_int
,
VME_ADDR_DIR_int
:
std_logic
;
constant
c_NUM_WB_MASTERS
:
integer
:
=
2
;
constant
c_NUM_WB_MASTERS
:
integer
:
=
3
;
constant
c_NUM_WB_SLAVES
:
integer
:
=
1
;
constant
c_MASTER_VME
:
integer
:
=
0
;
constant
c_SLAVE_GOLDEN
:
integer
:
=
0
;
constant
c_SLAVE_ONEWIRE
:
integer
:
=
1
;
constant
c_DESC_SYNTHESIS
:
integer
:
=
2
;
constant
c_DESC_REPO_URL
:
integer
:
=
3
;
constant
c_SLAVE_GPIO
:
integer
:
=
2
;
constant
c_DESC_SYNTHESIS
:
integer
:
=
3
;
constant
c_DESC_REPO_URL
:
integer
:
=
4
;
constant
c_INTERCONNECT_LAYOUT
:
t_sdb_record_array
(
c_NUM_WB_MASTERS
+
1
downto
0
)
:
=
(
c_SLAVE_GOLDEN
=>
f_sdb_embed_device
(
c_xwb_golden_sdb
,
x"00010000"
),
c_SLAVE_ONEWIRE
=>
f_sdb_embed_device
(
c_xwb_onewire_master_sdb
,
x"00012000"
),
c_SLAVE_GPIO
=>
f_sdb_embed_device
(
c_xwb_onewire_master_sdb
,
x"00013000"
),
c_DESC_SYNTHESIS
=>
f_sdb_embed_synthesis
(
c_sdb_synthesis_info
),
c_DESC_REPO_URL
=>
f_sdb_embed_repo_url
(
c_sdb_repo_url
)
);
...
...
@@ -214,7 +222,7 @@ architecture rtl of svec_top is
signal
powerup_reset_cnt
:
unsigned
(
7
downto
0
)
:
=
"00000000"
;
signal
powerup_rst_n
:
std_logic
:
=
'0'
;
signal
sys_locked
:
std_logic
;
signal
gpio_out
,
gpio_in
,
gpio_b
:
std_logic_vector
(
3
downto
0
);
begin
p_powerup_reset
:
process
(
clk_sys
)
...
...
@@ -422,6 +430,22 @@ begin
master_o
=>
cnx_master_out
);
xwb_gpio_port_1
:
entity
work
.
xwb_gpio_port
generic
map
(
g_interface_mode
=>
PIPELINED
,
g_address_granularity
=>
BYTE
,
g_num_pins
=>
4
,
g_with_builtin_tristates
=>
false
)
port
map
(
clk_sys_i
=>
clk_sys
,
rst_n_i
=>
local_reset_n
,
slave_i
=>
cnx_master_out
(
c_SLAVE_GPIO
),
slave_o
=>
cnx_master_in
(
c_SLAVE_GPIO
),
gpio_b
=>
gpio_b
,
gpio_out_o
=>
gpio_out
,
gpio_in_i
=>
gpio_in
,
gpio_oen_o
=>
open
);
U_Onewire
:
xwb_onewire_master
generic
map
(
g_interface_mode
=>
PIPELINED
,
...
...
@@ -457,6 +481,11 @@ begin
fmc_prsnt_n_i
(
1
)
=>
fmc1_prsntm2c_n_i
);
flash_mosi_o
<=
gpio_out
(
0
);
flash_sck_o
<=
gpio_out
(
1
);
flash_cs_n_o
<=
gpio_out
(
2
);
gpio_in
(
3
)
<=
flash_miso_i
;
end
rtl
;
hdl/top/golden/synthesis_descriptor.vhd
View file @
47d1cb6d
...
...
@@ -43,10 +43,10 @@ package synthesis_descriptor is
constant
c_sdb_synthesis_info
:
t_sdb_synthesis
:
=
(
syn_module_name
=>
"svec-golden "
,
syn_commit_id
=>
"
daf244bfc22002fbf68514441cd45c23
"
,
syn_commit_id
=>
"
1ac14fefeb80a390f0ac6a1a0f94c64a
"
,
syn_tool_name
=>
"ISE "
,
syn_tool_version
=>
x"00000133"
,
syn_date
=>
x"20140
204
"
,
syn_date
=>
x"20140
306
"
,
syn_username
=>
"twlostow "
);
constant
c_sdb_repo_url
:
t_sdb_repo_url
:
=
...
...
hdl/top/sfpga_bootloader/svec_sfpga_top.vhd
View file @
47d1cb6d
...
...
@@ -187,7 +187,9 @@ architecture rtl of svec_sfpga_top is
spi_cs_n_o
:
out
std_logic
;
spi_sclk_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
);
spi_miso_i
:
in
std_logic
;
flash_select_o
:
out
std_logic
);
end
component
;
component
chipscope_ila
...
...
@@ -237,8 +239,7 @@ architecture rtl of svec_sfpga_top is
signal
pll_reset_count
:
unsigned
(
15
downto
0
);
signal
spi_cs_n_int
,
spi_mosi_int
,
spi_sclk_int
:
std_logic
;
signal
pass_flash
:
std_logic
;
signal
flash_select
:
std_logic
;
begin
-- PLL for producing 83.3 MHz system clock (clk_sys) from a 20 MHz reference.
...
...
@@ -377,7 +378,8 @@ begin
spi_cs_n_o
=>
spi_cs_n_int
,
spi_sclk_o
=>
spi_sclk_int
,
spi_mosi_o
=>
spi_mosi_int
,
spi_miso_i
=>
spi_miso_i
);
spi_miso_i
=>
spi_miso_i
,
flash_select_o
=>
flash_select
);
-- produces a longer pulse on PROGRAM_B pin of the Application FPGA when
-- the VME bootloader mode is activated
...
...
@@ -439,9 +441,9 @@ begin
-- multiplex flash access between the AFPGA and SFPGA bootloader (if the
-- AFPGA is programmed, it's wired to the SPI flash).
spi_cs_n_o
<=
spi_cs_n_int
when
boot_done_i
=
'0'
else
afpga_flash_cs_n_i
;
spi_sclk_o
<=
spi_sclk_int
when
boot_done_i
=
'0'
else
afpga_flash_sck_i
;
spi_mosi_o
<=
spi_mosi_int
when
boot_done_i
=
'0'
else
afpga_flash_mosi_i
;
spi_cs_n_o
<=
spi_cs_n_int
when
flash_select
=
'1'
or
boot_done_i
=
'0'
else
afpga_flash_cs_n_i
;
spi_sclk_o
<=
spi_sclk_int
when
flash_select
=
'1'
or
boot_done_i
=
'0'
else
afpga_flash_sck_i
;
spi_mosi_o
<=
spi_mosi_int
when
flash_select
=
'1'
or
boot_done_i
=
'0'
else
afpga_flash_mosi_i
;
afpga_flash_miso_o
<=
spi_miso_i
;
-- When the VME bootloader is not active, do NOT drive any outputs and sit quiet.
...
...
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