hdl: golden firmware clock connection fix, updated to latest VME64x core

454096c4 · Tomasz Wlostowski · 92bd66ca · 454096c4 · 454096c4 · 454096c4
Commit 454096c4 authored Nov 29, 2012 by Tomasz Wlostowski
5 changed files
--- a/hdl/testbench/golden/Manifest.py
+++ b/hdl/testbench/golden/Manifest.py
+action = "simulation"
+target = "xilinx"
+fetchto = "../../ip_cores"
+vlog_opt="+incdir+../../sim/vme64x_bfm +incdir+../../sim/wb"
+
+files = [ "main.sv" ]
+
+modules = { "local" :  [ "../../top/golden" ] }
+
--- a/hdl/testbench/golden/main.sv
+++ b/hdl/testbench/golden/main.sv
+`include "vme64x_bfm.svh"
+`include "svec_vme_buffers.svh"
+
+module main;
+
+   reg rst_n = 0;
+   reg clk_20m = 0;
+   
+   always #25ns clk_20m <= ~clk_20m;
+   
+   initial begin
+      repeat(20) @(posedge clk_20m);
+      rst_n = 1;
+   end
+   
+   IVME64X VME(rst_n);
+
+   `DECLARE_VME_BUFFERS(VME.slave);
+
+   svec_top
+     
+     DUT (
+	  .clk_20m_vcxo_i(clk_20m),
+	  .rst_n_i(rst_n),
+     
+	  `WIRE_VME_PINS(8)
+  	  );
+
+   task automatic init_vme64x_core(ref CBusAccessor_VME64x acc);
+      uint64_t rv;
+      
+      /* map func0 to 0x80000000, A32 */
+
+      acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3);
+      acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
+      acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
+
+
+      acc.set_default_modifiers(A32 | D32 | SINGLE);
+   endtask // init_vme64x_core
+   
+   
+   initial begin
+      uint64_t d;
+      
+      int i, result;
+      
+      CBusAccessor_VME64x acc = new(VME.master);
+
+      
+      #20us;
+      init_vme64x_core(acc);
+
+
+      acc.read(0, d, A32|SINGLE|D32);
+      $display("Read0: %x\n", d);
+      
+   end
+
+  
+endmodule // main
+
+
+
--- a/hdl/testbench/golden/wave.do
+++ b/hdl/testbench/golden/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /main/rst_n
+add wave -noupdate /main/clk_20m
+add wave -noupdate /main/DUT/cnx_master_out
+add wave -noupdate /main/DUT/cnx_master_in
+add wave -noupdate /main/DUT/cnx_slave_out
+add wave -noupdate /main/DUT/cnx_slave_in
+add wave -noupdate /main/DUT/clk_20m_vcxo_i
+add wave -noupdate /main/DUT/rst_n_i
+add wave -noupdate /main/DUT/VME_AS_n_i
+add wave -noupdate /main/DUT/VME_RST_n_i
+add wave -noupdate /main/DUT/VME_WRITE_n_i
+add wave -noupdate /main/DUT/VME_AM_i
+add wave -noupdate /main/DUT/VME_DS_n_i
+add wave -noupdate /main/DUT/VME_GA_i
+add wave -noupdate /main/DUT/VME_BERR_o
+add wave -noupdate /main/DUT/VME_DTACK_n_o
+add wave -noupdate /main/DUT/VME_RETRY_n_o
+add wave -noupdate /main/DUT/VME_RETRY_OE_o
+add wave -noupdate /main/DUT/VME_LWORD_n_b
+add wave -noupdate /main/DUT/VME_ADDR_b
+add wave -noupdate /main/DUT/VME_DATA_b
+add wave -noupdate /main/DUT/VME_BBSY_n_i
+add wave -noupdate /main/DUT/VME_IRQ_n_o
+add wave -noupdate /main/DUT/VME_IACK_n_i
+add wave -noupdate /main/DUT/VME_IACKIN_n_i
+add wave -noupdate /main/DUT/VME_IACKOUT_n_o
+add wave -noupdate /main/DUT/VME_DTACK_OE_o
+add wave -noupdate /main/DUT/VME_DATA_DIR_o
+add wave -noupdate /main/DUT/VME_DATA_OE_N_o
+add wave -noupdate /main/DUT/VME_ADDR_DIR_o
+add wave -noupdate /main/DUT/VME_ADDR_OE_N_o
+add wave -noupdate /main/DUT/fmc0_prsntm2c_n_i
+add wave -noupdate /main/DUT/fmc1_prsntm2c_n_i
+add wave -noupdate /main/DUT/fmc0_scl_b
+add wave -noupdate /main/DUT/fmc0_sda_b
+add wave -noupdate /main/DUT/fmc1_scl_b
+add wave -noupdate /main/DUT/fmc1_sda_b
+add wave -noupdate /main/DUT/tempid_dq_b
+add wave -noupdate /main/DUT/VME_DATA_b_out
+add wave -noupdate /main/DUT/VME_ADDR_b_out
+add wave -noupdate /main/DUT/VME_LWORD_n_b_out
+add wave -noupdate /main/DUT/VME_DATA_DIR_int
+add wave -noupdate /main/DUT/VME_ADDR_DIR_int
+add wave -noupdate /main/DUT/cnx_master_out
+add wave -noupdate /main/DUT/cnx_master_in
+add wave -noupdate /main/DUT/cnx_slave_out
+add wave -noupdate /main/DUT/cnx_slave_in
+add wave -noupdate /main/DUT/fd0_scl_out
+add wave -noupdate /main/DUT/fd0_scl_in
+add wave -noupdate /main/DUT/fd0_sda_out
+add wave -noupdate /main/DUT/fd0_sda_in
+add wave -noupdate /main/DUT/fd1_scl_out
+add wave -noupdate /main/DUT/fd1_scl_in
+add wave -noupdate /main/DUT/fd1_sda_out
+add wave -noupdate /main/DUT/fd1_sda_in
+add wave -noupdate /main/DUT/wrc_owr_en
+add wave -noupdate /main/DUT/wrc_owr_in
+add wave -noupdate /main/DUT/pllout_clk_fb_sys
+add wave -noupdate /main/DUT/pllout_clk_sys
+add wave -noupdate /main/DUT/clk_20m_vcxo_buf
+add wave -noupdate /main/DUT/clk_sys
+add wave -noupdate /main/DUT/rst_n_a
+add wave -noupdate /main/DUT/local_reset_n
+add wave -noupdate /main/DUT/vme_master_out
+add wave -noupdate /main/DUT/vme_master_in
+add wave -noupdate /main/DUT/gpio_out
+add wave -noupdate /main/DUT/gpio_in
+add wave -noupdate /main/DUT/dummy_pins
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {19197436 ps} 0}
+configure wave -namecolwidth 177
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {1541628 ps} {36853244 ps}
--- a/hdl/top/golden/svec_top.vhd
+++ b/hdl/top/golden/svec_top.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2011-08-24
-- Last update: 2012-10-12
+-- Last update: 2012-11-29
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -181,7 +181,7 @@ architecture rtl of svec_top is
  signal pllout_clk_fb_sys, pllout_clk_sys : std_logic;
  signal clk_20m_vcxo_buf                  : std_logic;
  signal clk_sys                           : std_logic;
-  signal rst_n_a, local_reset_n            : std_logic;
+  signal local_reset_n            : std_logic;

  signal vme_master_out : t_wishbone_master_out;
  signal vme_master_in  : t_wishbone_master_in;
@@ -191,8 +191,32 @@ architecture rtl of svec_top is

  signal dummy_pins : std_logic_vector(1 downto 0);
  
+  signal powerup_reset_cnt : unsigned(7 downto 0) := "00000000";
+  signal powerup_rst_n     : std_logic            := '0';
+  signal sys_locked        : std_logic;
+  
 begin

+  p_powerup_reset : process(clk_sys)
+  begin
+    if rising_edge(clk_sys) then
+      if(VME_RST_n_i = '0' or rst_n_i = '0') then
+        powerup_rst_n <= '0';
+      elsif sys_locked = '1' then
+        if(powerup_reset_cnt = "11111111") then
+          powerup_rst_n <= '1';
+        else
+          powerup_rst_n     <= '0';
+          powerup_reset_cnt <= powerup_reset_cnt + 1;
+        end if;
+      else
+        powerup_rst_n     <= '0';
+        powerup_reset_cnt <= "00000000";
+      end if;
+    end if;
+  end process;
+
+
 -------------------------------------------------------------------------------
 -- Clock distribution/PLL and reset 
 -------------------------------------------------------------------------------
@@ -224,20 +248,24 @@ begin
      CLKOUT3  => open,
      CLKOUT4  => open,
      CLKOUT5  => open,
-      LOCKED   => open,
+      LOCKED   => sys_locked,
      RST      => '0',
      CLKFBIN  => pllout_clk_fb_sys,
      CLKIN    => clk_20m_vcxo_buf);

-  rst_n_a <= VME_RST_n_i and rst_n_i;

  U_Sync_Reset : gc_sync_ffs
    port map (
      clk_i    => clk_sys,
      rst_n_i  => '1',
-      data_i   => rst_n_a,
+      data_i   => powerup_rst_n,
      synced_o => local_reset_n);

+  U_cmp_clk_vcxo_buf : BUFG
+    port map (
+      O => clk_20m_vcxo_buf,
+      I => clk_20m_vcxo_i);
+  
  U_cmp_clk_sys_buf : BUFG
    port map (
      O => clk_sys,

--- a/hdl/top/golden/xvme64x_core.vhd
+++ b/hdl/top/golden/xvme64x_core.vhd
 library ieee;
 use ieee.STD_LOGIC_1164.all;
 use WORK.wishbone_pkg.all;
+use work.vme64x_pack.all;

 entity xvme64x_core is
  
@@ -49,11 +50,10 @@ end xvme64x_core;
 architecture wrapper of xvme64x_core is

  component VME64xCore_Top
-    generic(
-      g_width      : integer := 32;
-      g_addr_width : integer := 64;
-      g_CRAM_SIZE  : integer := 1024
-      );
+    generic (
+      g_wb_data_width      : integer := 32;
+      g_wb_addr_width : integer := 64;
+      g_CRAM_SIZE  : integer := 1024);
    port (
      clk_i           : in  std_logic;
      reset_o         : out std_logic;
@@ -66,13 +66,13 @@ architecture wrapper of xvme64x_core is
      VME_BERR_o      : out std_logic;
      VME_DTACK_n_o   : out std_logic;
      VME_RETRY_n_o   : out std_logic;
-      VME_LWORD_n_b_i : in  std_logic;
-      VME_LWORD_n_b_o : out std_logic;
-      VME_ADDR_b_i    : in  std_logic_vector(31 downto 1);
-      VME_ADDR_b_o    : out std_logic_vector(31 downto 1);
-      VME_DATA_b_i    : in  std_logic_vector(31 downto 0);
-      VME_DATA_b_o    : out std_logic_vector(31 downto 0);
-      VME_IRQ_n_o     : out std_logic_vector(6 downto 0);
+      VME_LWORD_n_i   : in  std_logic;
+      VME_LWORD_n_o   : out std_logic;
+      VME_ADDR_i      : in  std_logic_vector(31 downto 1);
+      VME_ADDR_o      : out std_logic_vector(31 downto 1);
+      VME_DATA_i      : in  std_logic_vector(31 downto 0);
+      VME_DATA_o      : out std_logic_vector(31 downto 0);
+      VME_IRQ_o       : out std_logic_vector(6 downto 0);
      VME_IACKIN_n_i  : in  std_logic;
      VME_IACK_n_i    : in  std_logic;
      VME_IACKOUT_n_o : out std_logic;
@@ -82,20 +82,20 @@ architecture wrapper of xvme64x_core is
      VME_ADDR_DIR_o  : out std_logic;
      VME_ADDR_OE_N_o : out std_logic;
      VME_RETRY_OE_o  : out std_logic;
-      DAT_i           : in  std_logic_vector(g_width - 1 downto 0);
-      DAT_o           : out std_logic_vector(g_width - 1 downto 0);
-      ADR_o           : out std_logic_vector(g_addr_width - 1 downto 0);
+      DAT_i           : in  std_logic_vector(g_wb_data_width - 1 downto 0);
+      DAT_o           : out std_logic_vector(g_wb_data_width - 1 downto 0);
+      ADR_o           : out std_logic_vector(g_wb_addr_width - 1 downto 0);
      CYC_o           : out std_logic;
      ERR_i           : in  std_logic;
      RTY_i           : in  std_logic;
-      SEL_o           : out std_logic_vector(g_width / 8 - 1 downto 0);
+      SEL_o           : out std_logic_vector(f_div8(g_wb_addr_width) - 1 downto 0);
      STB_o           : out std_logic;
      ACK_i           : in  std_logic;
      WE_o            : out std_logic;
      STALL_i         : in  std_logic;
-      INT_ack         : out std_logic;
+      INT_ack_o       : out std_logic;
      IRQ_i           : in  std_logic;
-      leds            : out std_logic_vector(7 downto 0));
+      debug           : out std_logic_vector(7 downto 0));
  end component;

  signal rst_in, rst_out          : std_logic;
@@ -121,13 +121,13 @@ begin  -- wrapper
      VME_DTACK_n_o   => VME_DTACK_n_o,
      VME_RETRY_n_o   => VME_RETRY_n_o,
      VME_RETRY_OE_o  => VME_RETRY_OE_o,
-      VME_LWORD_n_b_i => VME_LWORD_n_b_i,
-      VME_LWORD_n_b_o => VME_LWORD_n_b_o,
-      VME_ADDR_b_i    => VME_ADDR_b_i,
-      VME_ADDR_b_o    => VME_ADDR_b_o,
-      VME_DATA_b_i    => VME_DATA_b_i,
-      VME_DATA_b_o    => VME_DATA_b_o,
-      VME_IRQ_n_o     => VME_IRQ_n_o,
+      VME_LWORD_n_i => VME_LWORD_n_b_i,
+      VME_LWORD_n_o => VME_LWORD_n_b_o,
+      VME_ADDR_i    => VME_ADDR_b_i,
+      VME_ADDR_o    => VME_ADDR_b_o,
+      VME_DATA_i    => VME_DATA_b_i,
+      VME_DATA_o    => VME_DATA_b_o,
+      VME_IRQ_o     => VME_IRQ_n_o,
      VME_IACKIN_n_i  => VME_IACKIN_n_i,
      VME_IACK_n_i    => VME_IACK_n_i,
      VME_IACKOUT_n_o => VME_IACKOUT_n_o,
@@ -149,13 +149,16 @@ begin  -- wrapper
      WE_o    => master_o.we,
      STALL_i => master_i.stall,
      IRQ_i   => irq_i,
-      INT_ack => irq_ack_o);
+      INT_ack_o => irq_ack_o
+      );

  master_o.dat <= dat_out(31 downto 0);
  master_o.sel <= (others => '1');
  master_o.adr <= adr_out(29 downto 0) & "00";
  dat_in       <= master_i.dat;

+--  VME_IRQ_n_o <= (others => '0');
+  
  
  
 end wrapper;