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Simple VME FMC Carrier SVEC
Commit 43fa5537 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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parent bd991588
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Showing with 31 additions and 6 deletions
hdl/scripts/pins/xilinx_pin_assigner.py
View file @ 43fa5537
......@@ -203,8 +203,12 @@ class Design:
continue
if s.diff:
for idx in range( s.range_lo, s.range_hi + 1 ):
#print("Do Signal %s[%d]" % (s.name, idx))
print("Do Signal %s[%d]" % (s.name, idx))
self.fpga_pins.free_pins_in_banks(IOBankGroup([12,13,15]))
pair = self.signals.find_diff_pair( s )
print(pair)
#if pair != None and pair[0].done:
# continue
f_pair = self.fpga_pins.first_free_diff_pair( banks = s.banks )
if f_pair == None:
print("!!!! Unable to fit diff pair: %s" % s.name)
......@@ -253,6 +257,7 @@ class Design:
rstring = ""
else:
rstring = "[%d]" % idx
f_xdc.write("# PadFunction: %s\n"%s.fpga_pins[idx].name)
f_xdc.write("set_property PACKAGE_PIN %s [get_ports {%s%s}]\n" % (s.fpga_pins[idx].pad, s.name, rstring))
iostd = None
......@@ -462,10 +467,27 @@ design.signals.add("fmc1_clk_m2c_n_i[0]", force="IO_L12N_T1_MRCC_13", banks=bank
design.signals.add("fmc1_clk_m2c_p_i[1]", force="IO_L13P_T2_MRCC_13", banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc1_clk_m2c_n_i[1]", force="IO_L13P_T2_MRCC_13", banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc0_la_p_b", 33, 0, diff=True, banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc0_la_n_b", 33, 0, diff=True, banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc1_la_p_b", 33, 0, diff=True, banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc1_la_n_b", 33, 0, diff=True, banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc0_la_p_b[0]", force="IO_L12P_T1_MRCC_AD5P_15", banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc0_la_n_b[0]", force="IO_L12N_T1_MRCC_AD5N_15", banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc1_la_p_b[0]", force="IO_L13P_T2_MRCC_15", banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc1_la_n_b[0]", force="IO_L13N_T2_MRCC_15", banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc0_la_p_b[17]", force="IO_L11P_T1_SRCC_12", banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc0_la_n_b[17]", force="IO_L11N_T1_SRCC_12", banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc1_la_p_b[17]", force="IO_L11P_T1_SRCC_13", banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc1_la_n_b[17]", force="IO_L11N_T1_SRCC_13", banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc0_la_p_b", 16, 1, diff=True, banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc0_la_n_b", 16, 1, diff=True, banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc1_la_p_b", 16, 1, diff=True, banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc1_la_n_b", 16, 1, diff=True, banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc0_la_p_b", 33, 18, diff=True, banks=banks_fmc, iostandard="LVDS_25")
#design.signals.add("fmc0_la_n_b", 33, 18, diff=True, banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("fmc1_la_p_b", 33, 18, diff=True, banks=banks_fmc, iostandard="LVDS_25")
#design.signals.add("fmc1_la_n_b", 33, 18, diff=True, banks=banks_fmc, iostandard="LVDS_25")
design.signals.add("p2_b", 39, 0, diff=False, banks=banks_33, iostandard="LVCMOS25")
......@@ -576,6 +598,7 @@ design.signals.add("fmc1_tdo_i", banks=banks_33, iostandard="LVCMOS25")
design.signals.add("ioexp_reset_o", banks=banks_33, iostandard="LVCMOS25")
design.signals.add("ioexp_sclk_o", banks=banks_33, iostandard="LVCMOS25")
design.signals.add("ioexp_rclk_o", banks=banks_33, iostandard="LVCMOS25")
design.signals.add("ioexp_rclk_power_o", banks=banks_33, iostandard="LVCMOS25")
design.signals.add("ioexp_d_o", banks=banks_33, iostandard="LVCMOS25")
design.signals.add("ioexp_d_i", banks=banks_33, iostandard="LVCMOS25")
......
hdl/top/svec7_test/svec7_test_top.vhd
View file @ 43fa5537
......@@ -152,6 +152,7 @@ entity svec7_test_top is
-- I/O Expander for the slow pins
ioexp_sclk_o : out std_logic;
ioexp_rclk_o : out std_logic;
ioexp_rclk_power_o : out std_logic;
ioexp_d_o : out std_logic;
ioexp_reset_o : out std_logic;
ioexp_d_i : in std_logic;
......@@ -711,5 +712,6 @@ begin -- architecture arch
slave_i => cnx_slave_in(c_WB_SLAVE_CLOCK_MON),
slave_o => cnx_slave_out(c_WB_SLAVE_CLOCK_MON));
ioexp_rclk_power_o <= '0';
end architecture arch;
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