Skip to content

S
Simple VME FMC Carrier SVEC
Commit 39d8e652 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

svec7: test top level with all pins placed, passes P&R

parent 94c5a4ca
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 70224 additions and 1402 deletions
hdl/platform/xilinx/kintex7/svec7-mig/Manifest.py 0 → 100644
View file @ 39d8e652
files = [
"./clocking/mig_7series_v4_1_iodelay_ctrl.v",
"./clocking/mig_7series_v4_1_clk_ibuf.v",
"./clocking/mig_7series_v4_1_infrastructure.v",
"./clocking/mig_7series_v4_1_tempmon.v",
"./ip_top/mig_7series_v4_1_mem_intfc.v",
"./ip_top/mig_7series_v4_1_memc_ui_top_axi.v",
"./svec7_ddr_controller_mig_mig_sim.v",
"./ecc/mig_7series_v4_1_fi_xor.v",
"./ecc/mig_7series_v4_1_ecc_buf.v",
"./ecc/mig_7series_v4_1_ecc_dec_fix.v",
"./ecc/mig_7series_v4_1_ecc_gen.v",
"./ecc/mig_7series_v4_1_ecc_merge_enc.v",
"./phy/mig_7series_v4_1_ddr_phy_rdlvl.v",
"./phy/mig_7series_v4_1_poc_tap_base.v",
"./phy/mig_7series_v4_1_ddr_of_pre_fifo.v",
"./phy/mig_7series_v4_1_ddr_phy_ck_addr_cmd_delay.v",
"./phy/mig_7series_v4_1_ddr_phy_ocd_edge.v",
"./phy/mig_7series_v4_1_ddr_phy_wrlvl.v",
"./phy/mig_7series_v4_1_ddr_phy_dqs_found_cal.v",
"./phy/mig_7series_v4_1_poc_meta.v",
"./phy/mig_7series_v4_1_ddr_phy_wrlvl_off_delay.v",
"./phy/mig_7series_v4_1_poc_cc.v",
"./phy/mig_7series_v4_1_ddr_byte_group_io.v",
"./phy/mig_7series_v4_1_ddr_phy_ocd_mux.v",
"./phy/mig_7series_v4_1_ddr_phy_ocd_samp.v",
"./phy/mig_7series_v4_1_ddr_calib_top.v",
"./phy/mig_7series_v4_1_ddr_phy_prbs_rdlvl.v",
"./phy/mig_7series_v4_1_poc_edge_store.v",
"./phy/mig_7series_v4_1_ddr_phy_ocd_data.v",
"./phy/mig_7series_v4_1_ddr_phy_wrcal.v",
"./phy/mig_7series_v4_1_ddr_phy_ocd_cntlr.v",
"./phy/mig_7series_v4_1_ddr_phy_tempmon.v",
"./phy/mig_7series_v4_1_ddr_phy_ocd_lim.v",
"./phy/mig_7series_v4_1_ddr_mc_phy.v",
"./phy/mig_7series_v4_1_ddr_if_post_fifo.v",
"./phy/mig_7series_v4_1_ddr_prbs_gen.v",
"./phy/mig_7series_v4_1_ddr_phy_init.v",
"./phy/mig_7series_v4_1_ddr_phy_top.v",
"./phy/mig_7series_v4_1_ddr_phy_oclkdelay_cal.v",
"./phy/mig_7series_v4_1_poc_pd.v",
"./phy/mig_7series_v4_1_ddr_phy_ocd_po_cntlr.v",
"./phy/mig_7series_v4_1_ddr_phy_dqs_found_cal_hr.v",
"./phy/mig_7series_v4_1_ddr_skip_calib_tap.v",
"./phy/mig_7series_v4_1_poc_top.v",
"./phy/mig_7series_v4_1_ddr_byte_lane.v",
"./phy/mig_7series_v4_1_ddr_phy_4lanes.v",
"./phy/mig_7series_v4_1_ddr_mc_phy_wrapper.v",
"./controller/mig_7series_v4_1_bank_common.v",
"./controller/mig_7series_v4_1_mc.v",
"./controller/mig_7series_v4_1_arb_select.v",
"./controller/mig_7series_v4_1_arb_mux.v",
"./controller/mig_7series_v4_1_bank_queue.v",
"./controller/mig_7series_v4_1_bank_state.v",
"./controller/mig_7series_v4_1_arb_row_col.v",
"./controller/mig_7series_v4_1_round_robin_arb.v",
"./controller/mig_7series_v4_1_bank_mach.v",
"./controller/mig_7series_v4_1_col_mach.v",
"./controller/mig_7series_v4_1_bank_compare.v",
"./controller/mig_7series_v4_1_bank_cntrl.v",
"./controller/mig_7series_v4_1_rank_cntrl.v",
"./controller/mig_7series_v4_1_rank_mach.v",
"./controller/mig_7series_v4_1_rank_common.v",
"./axi/mig_7series_v4_1_axi_mc_r_channel.v",
"./axi/mig_7series_v4_1_axi_mc_simple_fifo.v",
"./axi/mig_7series_v4_1_axi_ctrl_reg.v",
"./axi/mig_7series_v4_1_ddr_carry_latch_and.v",
"./axi/mig_7series_v4_1_axi_mc_cmd_translator.v",
"./axi/mig_7series_v4_1_axi_ctrl_top.v",
"./axi/mig_7series_v4_1_ddr_w_upsizer.v",
"./axi/mig_7series_v4_1_axi_ctrl_write.v",
"./axi/mig_7series_v4_1_ddr_comparator.v",
"./axi/mig_7series_v4_1_ddr_axi_upsizer.v",
"./axi/mig_7series_v4_1_axi_mc_cmd_fsm.v",
"./axi/mig_7series_v4_1_ddr_carry_and.v",
"./axi/mig_7series_v4_1_ddr_axic_register_slice.v",
"./axi/mig_7series_v4_1_axi_ctrl_addr_decode.v",
"./axi/mig_7series_v4_1_axi_mc.v",
"./axi/mig_7series_v4_1_axi_mc_wr_cmd_fsm.v",
"./axi/mig_7series_v4_1_axi_ctrl_reg_bank.v",
"./axi/mig_7series_v4_1_ddr_command_fifo.v",
"./axi/mig_7series_v4_1_axi_mc_fifo.v",
"./axi/mig_7series_v4_1_ddr_carry_latch_or.v",
"./axi/mig_7series_v4_1_ddr_carry_or.v",
"./axi/mig_7series_v4_1_axi_mc_incr_cmd.v",
"./axi/mig_7series_v4_1_ddr_comparator_sel_static.v",
"./axi/mig_7series_v4_1_axi_mc_ar_channel.v",
"./axi/mig_7series_v4_1_axi_mc_cmd_arbiter.v",
"./axi/mig_7series_v4_1_axi_mc_b_channel.v",
"./axi/mig_7series_v4_1_ddr_a_upsizer.v",
"./axi/mig_7series_v4_1_axi_mc_w_channel.v",
"./axi/mig_7series_v4_1_axi_mc_aw_channel.v",
"./axi/mig_7series_v4_1_axi_mc_wrap_cmd.v",
"./axi/mig_7series_v4_1_ddr_r_upsizer.v",
"./axi/mig_7series_v4_1_axi_ctrl_read.v",
"./axi/mig_7series_v4_1_ddr_axi_register_slice.v",
"./axi/mig_7series_v4_1_ddr_comparator_sel.v",
"./svec7_ddr_controller_mig_mig.v",
"./svec7_ddr_controller_mig.v",
"./ui/mig_7series_v4_1_ui_rd_data.v",
"./ui/mig_7series_v4_1_ui_top.v",
"./ui/mig_7series_v4_1_ui_cmd.v",
"./ui/mig_7series_v4_1_ui_wr_data.v" ]
\ No newline at end of file
hdl/platform/xilinx/kintex7/svec7-mig/axi/mig_7series_v4_1_axi_ctrl_addr_decode.v 0 → 100644
View file @ 39d8e652
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_ctrl_ecc_top.v
//
// Description:
//
// Specifications:
//
// Structure:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_1_axi_ctrl_addr_decode #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AXI-4-Lite address bus
parameter integer C_ADDR_WIDTH = 32,
// Number of Registers
parameter integer C_NUM_REG = 5,
parameter integer C_NUM_REG_WIDTH = 3,
// Number of Registers
parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF,
parameter C_REG_RDWR_ARRAY = 5'b00101
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI4-Lite Slave Interface
// Slave Interface System Signals
input wire [C_ADDR_WIDTH-1:0] axaddr ,
// Slave Interface Write Data Ports
output wire [C_NUM_REG_WIDTH-1:0] reg_decode_num
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
function [C_ADDR_WIDTH-1:0] calc_bit_mask (
input [C_NUM_REG*C_ADDR_WIDTH-1:0] addr_decode_array
);
begin : func_calc_bit_mask
integer i;
reg [C_ADDR_WIDTH-1:0] first_addr;
reg [C_ADDR_WIDTH-1:0] bit_mask;
calc_bit_mask = {C_ADDR_WIDTH{1'b0}};
first_addr = addr_decode_array[C_ADDR_WIDTH+:C_ADDR_WIDTH];
for (i = 2; i < C_NUM_REG; i = i + 1) begin
bit_mask = first_addr ^ addr_decode_array[C_ADDR_WIDTH*i +: C_ADDR_WIDTH];
calc_bit_mask = calc_bit_mask | bit_mask;
end
end
endfunction
function integer lsb_mask_index (
input [C_ADDR_WIDTH-1:0] mask
);
begin : my_lsb_mask_index
lsb_mask_index = 0;
while ((lsb_mask_index < C_ADDR_WIDTH-1) && ~mask[lsb_mask_index]) begin
lsb_mask_index = lsb_mask_index + 1;
end
end
endfunction
function integer msb_mask_index (
input [C_ADDR_WIDTH-1:0] mask
);
begin : my_msb_mask_index
msb_mask_index = C_ADDR_WIDTH-1;
while ((msb_mask_index > 0) && ~mask[msb_mask_index]) begin
msb_mask_index = msb_mask_index - 1;
end
end
endfunction
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_ADDR_BIT_MASK = calc_bit_mask(C_REG_ADDR_ARRAY);
localparam P_MASK_LSB = lsb_mask_index(P_ADDR_BIT_MASK);
localparam P_MASK_MSB = msb_mask_index(P_ADDR_BIT_MASK);
localparam P_MASK_WIDTH = P_MASK_MSB - P_MASK_LSB + 1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
integer i;
(* rom_extract = "no" *)
reg [C_NUM_REG_WIDTH-1:0] reg_decode_num_i;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
always @(*) begin
reg_decode_num_i = {C_NUM_REG_WIDTH{1'b0}};
for (i = 1; i < C_NUM_REG; i = i + 1) begin : decode_addr
if ((axaddr[P_MASK_MSB:P_MASK_LSB] == C_REG_ADDR_ARRAY[i*C_ADDR_WIDTH+P_MASK_LSB+:P_MASK_WIDTH])
&& C_REG_RDWR_ARRAY[i] ) begin
reg_decode_num_i = i[C_NUM_REG_WIDTH-1:0];
end
end
end
assign reg_decode_num = reg_decode_num_i;
endmodule
`default_nettype wire
hdl/platform/xilinx/kintex7/svec7-mig/axi/mig_7series_v4_1_axi_ctrl_read.v 0 → 100644
View file @ 39d8e652
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_ctrl_read.v
//
// Description:
//
// Specifications:
//
// Structure:
// axi_ctrl_top
// axi_ctrl_write
// axi_ctrl_addr_decode
// axi_ctrl_read
// axi_ctrl_addr_decode
// axi_ctrl_reg_bank
// axi_ctrl_reg
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_1_axi_ctrl_read #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AXI-4-Lite address bus
parameter integer C_ADDR_WIDTH = 32,
// Width of AXI-4-Lite data buses
parameter integer C_DATA_WIDTH = 32,
// Number of Registers
parameter integer C_NUM_REG = 5,
parameter integer C_NUM_REG_WIDTH = 3,
// Number of Registers
parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF,
parameter C_REG_RDAC_ARRAY = 5'b11111
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI4-Lite Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Read Address Ports
input wire [C_ADDR_WIDTH-1:0] araddr ,
// Slave Interface Read Data Ports
output wire rvalid ,
input wire rready ,
output wire [C_DATA_WIDTH-1:0] rdata ,
output wire [1:0] rresp ,
input wire pending ,
// MC Internal Signals
input wire [C_DATA_WIDTH*C_NUM_REG-1:0] reg_bank_array
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_NUM_REG_WIDTH-1:0] reg_decode_num;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
mig_7series_v4_1_axi_ctrl_addr_decode #
(
.C_ADDR_WIDTH ( C_ADDR_WIDTH ) ,
.C_NUM_REG ( C_NUM_REG ) ,
.C_NUM_REG_WIDTH ( C_NUM_REG_WIDTH ) ,
.C_REG_ADDR_ARRAY ( C_REG_ADDR_ARRAY ) ,
.C_REG_RDWR_ARRAY ( C_REG_RDAC_ARRAY )
)
axi_ctrl_addr_decode_0
(
.axaddr ( araddr ) ,
.reg_decode_num ( reg_decode_num )
);
assign rdata = reg_bank_array[ reg_decode_num*32+:32];
assign rresp = 2'b0; // Okay
assign rvalid = pending;
endmodule
`default_nettype wire
hdl/platform/xilinx/kintex7/svec7-mig/axi/mig_7series_v4_1_axi_ctrl_reg.v 0 → 100644
View file @ 39d8e652
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_ctrl_reg.v
//
// Description:
// This is just a general register. It has two write enables and two data ins
// to simplify the operation. Typically one write enable (we) comes from the
// external interface and the second write enable is used for internal writing
// to the register. A mask parameter is used to only write to the bits that
// are used in the register.
//
// Specifications:
//
// Structure:
// axi_ctrl_top
// axi_ctrl_write
// axi_ctrl_addr_decode
// axi_ctrl_read
// axi_ctrl_addr_decode
// axi_ctrl_reg_bank
// axi_ctrl_reg
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_1_axi_ctrl_reg #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_REG_WIDTH = 32,
parameter integer C_DATA_WIDTH = 32,
parameter C_INIT = 32'h0,
parameter C_MASK = 32'h1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_REG_WIDTH-1:0] data_in ,
input wire we ,
input wire we_int ,
input wire [C_REG_WIDTH-1:0] data_in_int ,
output wire [C_DATA_WIDTH-1:0] data_out
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [C_REG_WIDTH-1:0] data;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
data <= C_INIT[0+:C_REG_WIDTH];
end
else if (we) begin
data <= data_in;
end
else if (we_int) begin
data <= data_in_int;
end
else begin
data <= data;
end
end
// Does not supprot case where P_MASK_LSB > 0
generate
if (C_REG_WIDTH == C_DATA_WIDTH) begin : assign_no_zero_pad
assign data_out = data;
end
else begin : assign_zero_pad
assign data_out = {{C_DATA_WIDTH-C_REG_WIDTH{1'b0}}, data};
end
endgenerate
endmodule
`default_nettype wire
hdl/platform/xilinx/kintex7/svec7-mig/axi/mig_7series_v4_1_axi_ctrl_write.v 0 → 100644
View file @ 39d8e652
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_ctrl_write.v
//
// Description:
//
// Specifications:
//
// Structure:
// axi_ctrl_top
// axi_ctrl_write
// axi_ctrl_addr_decode
// axi_ctrl_read
// axi_ctrl_addr_decode
// axi_ctrl_reg_bank
// axi_ctrl_reg
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_1_axi_ctrl_write #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AXI-4-Lite address bus
parameter integer C_ADDR_WIDTH = 32,
// Width of AXI-4-Lite data buses
parameter integer C_DATA_WIDTH = 32,
// Number of Registers
parameter integer C_NUM_REG = 5,
parameter integer C_NUM_REG_WIDTH = 3,
// Number of Registers
parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF,
parameter C_REG_WRAC_ARRAY = 5'b11111
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI4-Lite Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Read Address Ports
input wire awvalid ,
input wire awready ,
input wire [C_ADDR_WIDTH-1:0] awaddr ,
// Slave Interface Read Data Ports
input wire wvalid ,
output wire wready ,
input wire [C_DATA_WIDTH-1:0] wdata ,
output wire bvalid ,
input wire bready ,
output wire [1:0] bresp ,
// Internal Signals
output wire [C_NUM_REG_WIDTH-1:0] reg_data_sel ,
output wire reg_data_write ,
output wire [C_DATA_WIDTH-1:0] reg_data
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire awhandshake;
wire whandshake;
reg whandshake_d1;
wire bhandshake;
wire [C_NUM_REG_WIDTH-1:0] reg_decode_num;
reg awready_i;
reg wready_i;
reg bvalid_i;
reg [C_DATA_WIDTH-1:0] data;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// Handshake signals
assign awhandshake = awvalid & awready;
assign whandshake = wvalid & wready;
assign bhandshake = bvalid & bready;
mig_7series_v4_1_axi_ctrl_addr_decode #
(
.C_ADDR_WIDTH ( C_ADDR_WIDTH ) ,
.C_NUM_REG ( C_NUM_REG ) ,
.C_NUM_REG_WIDTH ( C_NUM_REG_WIDTH ) ,
.C_REG_ADDR_ARRAY ( C_REG_ADDR_ARRAY ) ,
.C_REG_RDWR_ARRAY ( C_REG_WRAC_ARRAY )
)
axi_ctrl_addr_decode_0
(
.axaddr ( awaddr ) ,
.reg_decode_num ( reg_decode_num )
);
// wchannel only accepts data after aw handshake
assign wready = wready_i;
always @(posedge clk) begin
if (reset) begin
wready_i <= 1'b0;
end
else begin
wready_i <= (awhandshake | wready_i) & ~whandshake;
end
end
// Data is registered but not latched (like awaddr) since it used a cycle later
always @(posedge clk) begin
data <= wdata;
end
// bresponse is sent after successful w handshake
assign bvalid = bvalid_i;
assign bresp = 2'b0; // Okay
always @(posedge clk) begin
if (reset) begin
bvalid_i <= 1'b0;
end
else begin
bvalid_i <= (whandshake | bvalid_i) & ~bhandshake;
end
end
// Assign internal signals
assign reg_data = data;
assign reg_data_write = whandshake_d1;
assign reg_data_sel = reg_decode_num;
always @(posedge clk) begin
whandshake_d1 <= whandshake;
end
endmodule
`default_nettype wire
hdl/platform/xilinx/kintex7/svec7-mig/axi/mig_7series_v4_1_axi_mc_b_channel.v 0 → 100644
View file @ 39d8e652
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_mc_b_channel.v
//
// Description:
// This module is responsible for returning the write response to the master
// that initiated the write. The write address channel module will push the
// transaction ID into a FIFO in the write response module after the
// completion of the address write phase of the transaction. If strict
// coherency is enabled (C_STRICT_COHERENCY == 1), then this module will
// monitor the MCB command/write FIFOs to determine when to send back the
// response. It will not send the response until it is guaranteed that the
// write has been committed completely to memory.
//
// ERROR RESPONSE
// If the MCB write channel indicates there is an error or write FIFO under
// run then the AXI SLVERR response is returned otherwise the OKAY response
// is returned.
//
// WRITE COHERENCY CHECKING
// The MCB hard block can have up to 6 independent ports to memory. If the
// MCB block is configured as single port or as multi-port with separate
// regions then write coherency logic is not required. In all other cases,
// once a transaction has been sent to the MCB CMD channel, it is not
// guaranteed that it will commit to memory before a transaction on another
// port. To ensure that the response is only sent after the data has been
// written to external memory the write response will not be sent until
// either the write data FIFO is empty or that the command FIFO is empty.
//
// Assertions:
// 1. Standard FIFO assertions on bid_fifo_0.
// 2. bvalid == 0, when C_STRICT_COHERENCY == 1 and mcb_empty == 0.
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_1_axi_mc_b_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire reset,
// AXI signals
output wire [C_ID_WIDTH-1:0] bid,
output wire [1:0] bresp,
output wire bvalid,
input wire bready,
// Signals to/from the axi_mc_aw_channel modules
input wire b_push,
input wire [C_ID_WIDTH-1:0] b_awid,
input wire b_resp_rdy,
output wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// FIFO settings
localparam P_WIDTH = C_ID_WIDTH;
localparam P_DEPTH = 8;
localparam P_AWIDTH = 3;
// AXI protocol responses:
localparam P_OKAY = 2'b00;
localparam P_EXOKAY = 2'b01;
localparam P_SLVERR = 2'b10;
localparam P_DECERR = 2'b11;
localparam B_RESP_PERF = 1'b1; // Set to 1 to increase the write response performance for back to back single beats.
// Set to 0 in case of timing issues, but performance degrades for back to back single beats.
wire empty;
wire bhandshake;
wire [C_ID_WIDTH-1:0] bid_i;
reg b_pop;
reg bvalid_i;
reg [C_ID_WIDTH-1:0] bid_t;
assign bresp = P_OKAY;
generate
if (B_RESP_PERF == 1) begin
assign bid = bid_t;
assign bvalid = bvalid_i;
assign bhandshake = ~bvalid | bready;
always @(*)
b_pop = bhandshake & ~empty;
always @(posedge clk) begin
if(reset) begin
bid_t <= 'b0;
bvalid_i <= 1'b0;
end else if(bhandshake) begin
bid_t <= bid_i;
bvalid_i <= ~empty;
end
end
end else begin // B_RESP_PERF
assign bid = bid_i;
assign bvalid = bvalid_i;
assign bhandshake = bvalid & bready;
always @(posedge clk)
b_pop <= bhandshake;
always @(posedge clk) begin
if (reset | bhandshake) begin
bvalid_i <= 1'b0;
end else if (~empty & (~b_pop)) begin
bvalid_i <= 1'b1;
end
end
end // B_RESP_PERF
endgenerate
mig_7series_v4_1_axi_mc_fifo #
(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
bid_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( b_push ) ,
.rd_en ( b_pop ) ,
.din ( b_awid ) ,
.dout ( bid_i ) ,
.a_full ( ) ,
.full ( b_full ) ,
.a_empty ( ) ,
.empty ( empty )
);
endmodule
`default_nettype wire
hdl/platform/xilinx/kintex7/svec7-mig/axi/mig_7series_v4_1_axi_mc_cmd_fsm.v 0 → 100644
View file @ 39d8e652
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_mc_cmd_fsm.v
//
// Description:
// Simple state machine to handle sending commands from AXI to MC. The flow:
// 1. A transaction can only be initiaited when axvalid is true and data_rdy
// is true. For writes, data_rdy means that one completed BL8 or BL4 write
// data has been pushed into the MC write FIFOs. For read operations,
// data_rdy indicates that there is enough room to push the transaction into
// the read FIF & read transaction fifo in the shim. If the FIFO's in the
// read channel module is full, then the state machine waits for the
// FIFO's to drain out.
//
// 2. When CMD_EN is asserted, it remains high until we sample CMD_FULL in
// a low state. When CMD_EN == 1'b1, and CMD_FULL == 1'b0, then the command
// has been accepted. When the command is accepted, if the next_pending
// signal is high we will incremented to the next transaction and issue the
// cmd_en again when data_rdy is high. Otherwise we will go to the done
// state.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_1_axi_mc_cmd_fsm #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// MC burst length. = 1 for BL4 or BC4, = 2 for BL8
parameter integer C_MC_BURST_LEN = 1,
// parameter to identify rd or wr instantation
// = 1 rd , = 0 wr
parameter integer C_MC_RD_INST = 0
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output reg axready ,
input wire axvalid ,
output wire cmd_en ,
input wire cmd_full ,
// signal to increment to the next mc transaction
output wire next ,
// signal to the fsm there is another transaction required
input wire next_pending ,
// Write Data portion has completed or Read FIFO has a slot available (not
// full)
input wire data_rdy ,
// status signal for w_channel when command is written.
output wire cmd_en_last
);
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
assign cmd_en = (axvalid & data_rdy);
assign next = (~cmd_full & cmd_en);
assign cmd_en_last = next & ~next_pending;
always @(posedge clk) begin
if (reset)
axready <= 1'b0;
else
axready <= ~axvalid | cmd_en_last;
end
endmodule
`default_nettype wire
hdl/platform/xilinx/kintex7/svec7-mig/axi/mig_7series_v4_1_axi_mc_cmd_translator.v 0 → 100644
View file @ 39d8e652
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_mc_cmd_translator.v
//
// Description:
// INCR and WRAP burst modes are decoded in parallel and then the output is
// chosen based on the AxBURST value. FIXED burst mode is not supported and
// is mapped to the INCR command instead.
//
// Specifications:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_1_axi_mc_cmd_translator #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of cmd_byte_addr
// Range: 30
parameter integer C_MC_ADDR_WIDTH = 30,
// Width of AXI xDATA and MC xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32,
// MC burst length. = 1 for BL4 or BC4, = 2 for BL8
parameter integer C_MC_BURST_LEN = 1,
// DRAM clock to AXI clock ratio
// supported values 2, 4
parameter integer C_MC_nCK_PER_CLK = 2,
// Static value of axsize
// Range: 2-5
parameter integer C_AXSIZE = 2,
// Instance for Read channel or write channel
parameter integer C_MC_RD_INST = 0
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_AXI_ADDR_WIDTH-1:0] axaddr ,
input wire [7:0] axlen ,
input wire [2:0] axsize ,
input wire [1:0] axburst ,
input wire axvalid ,
input wire axready ,
output wire [C_MC_ADDR_WIDTH-1:0] cmd_byte_addr ,
output wire ignore_begin ,
output wire ignore_end ,
// Connections to/from fsm module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output wire next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_MC_BURST_MASK = {C_MC_ADDR_WIDTH{1'b1}} ^
{C_MC_BURST_LEN+(C_MC_nCK_PER_CLK/2){1'b1}};
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_AXI_ADDR_WIDTH-1:0] cmd_byte_addr_i;
wire [C_AXI_ADDR_WIDTH-1:0] axi_mc_incr_cmd_byte_addr;
wire incr_next_pending;
wire [C_AXI_ADDR_WIDTH-1:0] axi_mc_wrap_cmd_byte_addr;
wire wrap_next_pending;
wire incr_ignore_begin;
wire incr_ignore_end;
wire wrap_ignore_begin;
wire wrap_ignore_end;
wire axhandshake;
wire incr_axhandshake;
wire wrap_axhandshake;
wire incr_next;
wire wrap_next;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign axhandshake = axvalid & axready;
// INCR and WRAP translations are calcuated in independently, select the one
// for our transactions
// right shift by the UI width to the DRAM width ratio
assign cmd_byte_addr = (C_MC_nCK_PER_CLK == 4) ?
(cmd_byte_addr_i >> C_AXSIZE-3) & P_MC_BURST_MASK :
(cmd_byte_addr_i >> C_AXSIZE-2) & P_MC_BURST_MASK;
assign cmd_byte_addr_i = (axburst[1]) ? axi_mc_wrap_cmd_byte_addr : axi_mc_incr_cmd_byte_addr;
assign ignore_begin = (axburst[1]) ? wrap_ignore_begin : incr_ignore_begin;
assign ignore_end = (axburst[1]) ? wrap_ignore_end : incr_ignore_end;
assign next_pending = (axburst[1]) ? wrap_next_pending : incr_next_pending;
assign incr_axhandshake = (axburst[1]) ? 1'b0 : axhandshake;
assign wrap_axhandshake = (axburst[1]) ? axhandshake : 1'b0;
assign incr_next = (axburst[1]) ? 1'b0 : next;
assign wrap_next = (axburst[1]) ? next : 1'b0;
mig_7series_v4_1_axi_mc_incr_cmd #
(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_MC_ADDR_WIDTH (C_MC_ADDR_WIDTH),
.C_DATA_WIDTH (C_DATA_WIDTH),
.C_MC_BURST_LEN (C_MC_BURST_LEN),
.C_AXSIZE (C_AXSIZE),
.C_MC_RD_INST (C_MC_RD_INST)
)
axi_mc_incr_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( axaddr ) ,
.axlen ( axlen ) ,
.axsize ( axsize ) ,
.axhandshake ( incr_axhandshake ) ,
.cmd_byte_addr ( axi_mc_incr_cmd_byte_addr ) ,
.ignore_begin ( incr_ignore_begin ) ,
.ignore_end ( incr_ignore_end ) ,
.next ( incr_next ) ,
.next_pending ( incr_next_pending )
);
mig_7series_v4_1_axi_mc_wrap_cmd #
(
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_MC_ADDR_WIDTH (C_MC_ADDR_WIDTH),
.C_MC_BURST_LEN (C_MC_BURST_LEN),
.C_DATA_WIDTH (C_DATA_WIDTH),
.C_AXSIZE (C_AXSIZE),
.C_MC_RD_INST (C_MC_RD_INST)
)
axi_mc_wrap_cmd_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.axaddr ( axaddr ) ,
.axlen ( axlen ) ,
.axsize ( axsize ) ,
.axhandshake ( wrap_axhandshake ) ,
.ignore_begin ( wrap_ignore_begin ) ,
.ignore_end ( wrap_ignore_end ) ,
.cmd_byte_addr ( axi_mc_wrap_cmd_byte_addr ) ,
.next ( wrap_next ) ,
.next_pending ( wrap_next_pending )
);
endmodule
`default_nettype wire
hdl/platform/xilinx/kintex7/svec7-mig/axi/mig_7series_v4_1_axi_mc_fifo.v 0 → 100644
View file @ 39d8e652
//-----------------------------------------------------------------------------
//-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//Purpose:
// Synchronous, shallow FIFO that uses simple as a DP Memory.
// This requires about 1/2 the resources as a Distributed RAM DPRAM
// implementation.
//
// This FIFO will have the current data on the output when data is contained
// in the FIFO. When the FIFO is empty, the output data is invalid.
//
//Reference:
//Revision History:
//
//-----------------------------------------------
//
// MODULE: axi_mc_fifo
//
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
module mig_7series_v4_1_axi_mc_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = 0;
localparam [C_AWIDTH-1:0] C_FULL = C_DEPTH - 1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = C_DEPTH -2;
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH:0] cnt_read;
reg [C_AWIDTH:0] next_cnt_read;
wire [C_AWIDTH:0] cnt_read_plus1;
wire [C_AWIDTH:0] cnt_read_minus1;
wire [C_AWIDTH-1:0] read_addr;
///////////////////////////////////////
// Main FIFO Array
///////////////////////////////////////
assign read_addr = cnt_read;
assign dout = memory[read_addr];
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else cnt_read <= next_cnt_read;
end
assign cnt_read_plus1 = cnt_read + 1'b1;
assign cnt_read_minus1 = cnt_read - 1'b1;
always @(*) begin
next_cnt_read = cnt_read;
if ( wr_en & !rd_en) next_cnt_read = cnt_read_plus1;
else if (!wr_en & rd_en) next_cnt_read = cnt_read_minus1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = (cnt_read == C_FULL_PRE);
assign a_empty = (cnt_read == C_EMPTY_PRE);
endmodule // axi_mc_fifo
`default_nettype wire
hdl/rtl/svec7/svec7_base_wr.vhd
View file @ 39d8e652
This diff is collapsed.
hdl/rtl/svec_base_wr.vhd
View file @ 39d8e652
This diff is collapsed.
hdl/scripts/pins/xc7k160tfbg676pkg.txt 0 → 100644
View file @ 39d8e652
This diff is collapsed.
hdl/scripts/pins/xilinx_pin_assigner.py 0 → 100755
View file @ 39d8e652
This diff is collapsed.
hdl/syn/common/svec_base_common.ucf
View file @ 39d8e652
This diff is collapsed.
hdl/syn/golden/Manifest.py
View file @ 39d8e652
This diff is collapsed.
hdl/syn/svec7_test/Manifest.py
View file @ 39d8e652
This diff is collapsed.
hdl/testbench/svec7_bridge/Manifest.py
View file @ 39d8e652
This diff is collapsed.
hdl/testbench/svec7_bridge/glbl.v 0 → 100644
View file @ 39d8e652
This diff is collapsed.
hdl/testbench/svec7_bridge/main.sv
View file @ 39d8e652
This diff is collapsed.
hdl/testbench/svec7_bridge/run.do
View file @ 39d8e652
This diff is collapsed.
hdl/testbench/svec7_bridge/wave.do
View file @ 39d8e652
This diff is collapsed.
hdl/top/golden/svec_golden.vhd
View file @ 39d8e652
This diff is collapsed.
hdl/top/sfpga_bootloader/svec_sfpga_top.vhd
View file @ 39d8e652
This diff is collapsed.
hdl/top/svec7_sfpga/svec7_sfpga_top.ucf
View file @ 39d8e652
This diff is collapsed.
hdl/top/svec7_sfpga/svec7_sfpga_top.vhd
View file @ 39d8e652
This diff is collapsed.
hdl/top/svec7_test/Manifest.py
View file @ 39d8e652
This diff is collapsed.
hdl/top/svec7_test/svec7_test_top.vhd
View file @ 39d8e652
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment