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Simple VME FMC Carrier SVEC
Commit 270aca9d authored by Greg's avatar Greg
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circuit_board/SVEC/PCB-Layout/EDA-02030-V1-0_pcb.pcbdocPreview 0 → 100644
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circuit_board/SVEC/PCB-Layout/SVFC.pcbdocPreview 0 → 100644
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circuit_board/SVEC/SVEC.OutJob 0 → 100644
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circuit_board/SVEC/SVEC.PrjPcb 0 → 100644
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circuit_board/SVEC/SVEC.PrjPcbStructure 0 → 100644
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Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_AFPGA_power|SchDesignator=U_AFPGA_power|FileName=AFPGA_power.SchDoc|SymbolType=Normal|RawFileName=AFPGA_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_ClkGeneration|SchDesignator=U_ClkGeneration|FileName=ClkGeneration.SchDoc|SymbolType=Normal|RawFileName=ClkGeneration.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
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Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_FrontPannel|SchDesignator=U_FrontPannel|FileName=FrontPannel.SchDoc|SymbolType=Normal|RawFileName=FrontPannel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_JTAG&CONFIG|SchDesignator=U_JTAG&CONFIG|FileName=JTAG&CONFIG.SchDoc|SymbolType=Normal|RawFileName=JTAG&CONFIG.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_PowerSupplies|SchDesignator=U_PowerSupplies|FileName=PowerSupplies.SchDoc|SymbolType=Normal|RawFileName=PowerSupplies.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
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Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_SFPGA_power|SchDesignator=U_SFPGA_power|FileName=SFPGA_power.SchDoc|SymbolType=Normal|RawFileName=SFPGA_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_USB|SchDesignator=U_USB|FileName=USB.SchDoc|SymbolType=Normal|RawFileName=USB.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_VmeConnectors|SchDesignator=U_VmeConnectors|FileName=VmeConnectors.SchDoc|SymbolType=Normal|RawFileName=VmeConnectors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=TopLevelDocument|FileName=SVEC_TOP.SchDoc
Record=FPGA_COMPONENT|BaseComponentDesignator=IC40|DocumentName=SFPGA.SchDoc|LibraryReference=XC6SLX9-2FTG256C|SubProjectPath= |Configuration= |Description=Spartan-6 LX 1.2V FPGA, 186 User I/Os, 256-Ball Fine-Pitch Thin BGA (1.0mm Pitch), Speed Grade 2, Commercial Grade, Pb-Free|NexusDeviceId=XC6SLX9-2FTG256C|SubPartUniqueId1=QTOJQSMD|SubPartDocPath1=SFPGA.SchDoc|SubPartUniqueId2=AOYRMHFT|SubPartDocPath2=SFPGA.SchDoc|SubPartUniqueId3=OLSNOCAD|SubPartDocPath3=SFPGA.SchDoc|SubPartUniqueId4=LFMNKHSD|SubPartDocPath4=SFPGA.SchDoc|SubPartUniqueId5=ODYKENES|SubPartDocPath5=JTAG&CONFIG.SchDoc|SubPartUniqueId6=WVUDHYEK|SubPartDocPath6=SFPGA_power.SchDoc|SubPartUniqueId7=FATYVDMF|SubPartDocPath7=SFPGA_power.SchDoc
circuit_board/SVEC/SVFC.PrjPcbStructure 0 → 100644
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Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_AFPGA|SchDesignator=U_AFPGA|FileName=AFPGA.SchDoc|SymbolType=Normal|RawFileName=AFPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_AFPGA_power|SchDesignator=U_AFPGA_power|FileName=AFPGA_power.SchDoc|SymbolType=Normal|RawFileName=AFPGA_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_ClkGeneration|SchDesignator=U_ClkGeneration|FileName=ClkGeneration.SchDoc|SymbolType=Normal|RawFileName=ClkGeneration.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_DDR3_1|SchDesignator=U_DDR3_1|FileName=DDR3.SchDoc|SymbolType=Normal|RawFileName=DDR3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_DDR3_2|SchDesignator=U_DDR3_2|FileName=DDR3_2.SchDoc|SymbolType=Normal|RawFileName=DDR3_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_FmcConnectors|SchDesignator=U_FmcConnectors|FileName=FmcConnector.SchDoc|SymbolType=Normal|RawFileName=FmcConnector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_fpga_gtp|SchDesignator=U_fpga_gtp|FileName=fpga_gtp.SchDoc|SymbolType=Normal|RawFileName=fpga_gtp.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_FrontPannel|SchDesignator=U_FrontPannel|FileName=FrontPannel.SchDoc|SymbolType=Normal|RawFileName=FrontPannel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_JTAG&CONFIG|SchDesignator=U_JTAG&CONFIG|FileName=JTAG&CONFIG.SchDoc|SymbolType=Normal|RawFileName=JTAG&CONFIG.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_PowerSupplies|SchDesignator=U_PowerSupplies|FileName=PowerSupplies.SchDoc|SymbolType=Normal|RawFileName=PowerSupplies.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_SFPGA|SchDesignator=U_SFPGA|FileName=SFPGA.SchDoc|SymbolType=Normal|RawFileName=SFPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_SFPGA_power|SchDesignator=U_SFPGA_power|FileName=SFPGA_power.SchDoc|SymbolType=Normal|RawFileName=SFPGA_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_USB|SchDesignator=U_USB|FileName=USB.SchDoc|SymbolType=Normal|RawFileName=USB.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=VMEFMC.SchDoc|Designator=U_VmeConnectors|SchDesignator=U_VmeConnectors|FileName=VmeConnectors.SchDoc|SymbolType=Normal|RawFileName=VmeConnectors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=TopLevelDocument|FileName=VMEFMC.SchDoc
Record=FPGA_COMPONENT|BaseComponentDesignator=IC40|DocumentName=SFPGA.SchDoc|LibraryReference=XC6SLX9-2FTG256C|SubProjectPath= |Configuration= |Description=Spartan-6 LX 1.2V FPGA, 186 User I/Os, 256-Ball Fine-Pitch Thin BGA (1.0mm Pitch), Speed Grade 2, Commercial Grade, Pb-Free|NexusDeviceId=XC6SLX9-2FTG256C|SubPartUniqueId1=UTYDQHRM|SubPartDocPath1=SFPGA.SchDoc|SubPartUniqueId2=ASWFUJMY|SubPartDocPath2=SFPGA.SchDoc|SubPartUniqueId3=YBGBHHKV|SubPartDocPath3=SFPGA.SchDoc|SubPartUniqueId4=HBHDXTNI|SubPartDocPath4=SFPGA.SchDoc|SubPartUniqueId5=ODYKENES|SubPartDocPath5=JTAG&CONFIG.SchDoc|SubPartUniqueId6=CQRRUQEQ|SubPartDocPath6=SFPGA_power.SchDoc|SubPartUniqueId7=YPGBLSCB|SubPartDocPath7=SFPGA_power.SchDoc
circuit_board/SVEC/Schematics/AFPGA.SchDocPreview 0 → 100644
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circuit_board/SVEC/Schematics/AFPGA_power.SchDocPreview 0 → 100644
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circuit_board/SVEC/Schematics/ClkGeneration.SchDocPreview 0 → 100644
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circuit_board/SVEC/Schematics/DDR3.SchDocPreview 0 → 100644
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circuit_board/SVEC/Schematics/DDR3_2.SchDocPreview 0 → 100644
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circuit_board/SVEC/Schematics/FMC_CONNECTORS.SchDocPreview 0 → 100644
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circuit_board/SVEC/Schematics/FmcConnector..SchDocPreview 0 → 100644
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circuit_board/SVEC/Schematics/FmcConnector.SchDocPreview 0 → 100644
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circuit_board/SVEC/Schematics/FrontPannel.SchDocPreview 0 → 100644
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circuit_board/SVEC/Schematics/JTAG&CONFIG.SchDocPreview 0 → 100644
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circuit_board/SVEC/Schematics/PowerSupplies SCH ECO 2012-01-11 02-14-11.LOG 0 → 100644
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circuit_board/SVEC/Schematics/PowerSupplies SCH ECO 2012-01-11 02-14-16.LOG 0 → 100644
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