Merge branch '15-release_v3.0.0' into 'master'

Resolve "Make v3.0.0 release" Closes #15 See merge request be-cem-edl/fec/hardware-modules/svec!12

Merge branch '15-release_v3.0.0' into 'master'
Resolve "Make v3.0.0 release" Closes #15 See merge request be-cem-edl/fec/hardware-modules/svec!12
190e95de · Dimitris Lampridis · 8c43259e · c91efa5e · 190e95de · 190e95de
Commit 190e95de authored Dec 05, 2022 by Dimitris Lampridis
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CHANGELOG.rst CHANGELOG.rst +28 -0

conf.py doc/conf.py +1 -1

requirements.txt doc/requirements.txt +6 -0

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--- a/CHANGELOG.rst
+++ b/CHANGELOG.rst
@@ -6,6 +6,34 @@
 Change Log
 ==========

+3.0.0 - 2022-12-05
+==================
+Added
+-----
+- ci: better automation
+- sw: support for Linux 5.10
+
+Removed
+-------
+- hdl: unused and obsolete top-levels and simulations
+- hdl: Xilinx chipscope for SFPGA (files were actually for AFPGA)
+
+Changed
+-------
+- hdl: 'golden_wr' top-level renamed to 'wr_example'
+- hdl: 'template' testbench now used for simulating the golden top-level
+- sw|API change: the API to flash a bitstream moved from debugfs to sysfs. The
+  Linux kernel community removed API we used. The same behavior was achievable
+  only using sysfs.
+- bld: improved Makefiles
+
+Fixed
+-----
+- hdl: building of all top-levels
+- hdl: missing ddr and wr-cores dependencies
+- hdl: corrected and re-enabled timing constraints
+- hdl: location of general-cores in rtl Manifest
+
 2.0.4 - 2021-07-29
 ==================
 Fixed

--- a/doc/conf.py
+++ b/doc/conf.py
@@ -24,7 +24,7 @@
 # -- Project information -----------------------------------------------------

 project = 'SVEC'
-copyright = '2019, Federico Vaga <federico.vaga@cern.ch>'
+copyright = '2019, CERN (home.cern)'
 author = 'Federico Vaga <federico.vaga@cern.ch>'

 # -- General configuration ---------------------------------------------------

--- a/doc/requirements.txt
+++ b/doc/requirements.txt
+# SPDX-FileCopyrightText: 2022 CERN
+#
+# SPDX-License-Identifier: CC-BY-SA-4.0+
+
+sphinx
+sphinx_rtd_theme