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Simple VME FMC Carrier SVEC
Commit 169d707d authored by Tristan Gingold's avatar Tristan Gingold
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vme16_test: cleanup.

parent 5559e1ec
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Showing with 2 additions and 94 deletions
hdl/top/vme16_test/svec_vmecore_test_top.vhd
View file @ 169d707d
......@@ -59,12 +59,6 @@ entity svec_vmecore_test_top is
-- Local oscillators
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
-- clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
-- clk_125m_pllref_n_i : in std_logic;
-- clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
-- clk_125m_gtp_p_i : in std_logic;
---------------------------------------------------------------------------
-- VME interface
---------------------------------------------------------------------------
......@@ -93,63 +87,6 @@ entity svec_vmecore_test_top is
vme_am_i : in std_logic_vector(5 downto 0);
vme_addr_b : inout std_logic_vector(31 downto 1);
---------------------------------------------------------------------------
-- SPI interfaces to DACs
---------------------------------------------------------------------------
-- pll20dac_din_o : out std_logic;
-- pll20dac_sclk_o : out std_logic;
-- pll20dac_sync_n_o : out std_logic;
-- pll25dac_din_o : out std_logic;
-- pll25dac_sclk_o : out std_logic;
-- pll25dac_sync_n_o : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
-- sfp_txp_o : out std_logic;
-- sfp_txn_o : out std_logic;
-- sfp_rxp_i : in std_logic;
-- sfp_rxn_i : in std_logic;
-- sfp_mod_def0_i : in std_logic; -- sfp detect
-- sfp_mod_def1_b : inout std_logic; -- scl
-- sfp_mod_def2_b : inout std_logic; -- sda
-- sfp_rate_select_o : out std_logic;
-- sfp_tx_fault_i : in std_logic;
-- sfp_tx_disable_o : out std_logic;
-- sfp_los_i : in std_logic;
---------------------------------------------------------------------------
-- Carrier I2C EEPROM
---------------------------------------------------------------------------
-- carrier_scl_b : inout std_logic;
-- carrier_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
-- onewire_b : inout std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
-- uart_rxd_i : in std_logic;
-- uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- SPI (flash is connected to SFPGA and routed to AFPGA
-- once the boot process is complete)
---------------------------------------------------------------------------
-- spi_sclk_o : out std_logic;
-- spi_ncs_o : out std_logic;
-- spi_mosi_o : out std_logic;
-- spi_miso_i : in std_logic;
---------------------------------------------------------------------------
-- Carrier front panel LEDs and IOs
---------------------------------------------------------------------------
......@@ -157,15 +94,6 @@ entity svec_vmecore_test_top is
fp_led_line_oen_o : out std_logic_vector(1 downto 0);
fp_led_line_o : out std_logic_vector(1 downto 0);
fp_led_column_o : out std_logic_vector(3 downto 0)
-- fp_gpio1_o : out std_logic; -- PPS output
-- fp_gpio2_o : out std_logic; -- Ref clock div2 output
-- fp_gpio3_i : in std_logic; -- ext 10MHz clock input
-- fp_gpio4_i : in std_logic; -- ext PPS intput
-- fp_term_en_o : out std_logic_vector(4 downto 1);
-- fp_gpio1_a2b_o : out std_logic;
-- fp_gpio2_a2b_o : out std_logic;
-- fp_gpio34_a2b_o : out std_logic
);
end entity svec_vmecore_test_top;
......@@ -176,13 +104,6 @@ architecture top of svec_vmecore_test_top is
signal master_out : t_wishbone_master_out;
signal master_in : t_wishbone_master_in;
-- clock and reset
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal clk_ref_125m : std_logic;
signal clk_ref_div2 : std_logic;
signal clk_ext_ref : std_logic;
-- VME
signal vme_data_b_out : std_logic_vector(31 downto 0);
signal vme_addr_b_out : std_logic_vector(31 downto 1);
......@@ -194,9 +115,6 @@ architecture top of svec_vmecore_test_top is
signal vme_irq_n_o : std_logic_vector(7 downto 1);
-- LEDs and GPIO
signal pps : std_logic;
signal pps_led : std_logic;
signal pps_ext_in : std_logic;
signal svec_led : std_logic_vector(15 downto 0);
signal pllout_clk_fb_sys, pllout_clk_sys : std_logic;
......@@ -292,11 +210,12 @@ begin -- architecture top
vme_berr_o <= not vme_berr_n_o;
vme_irq_o <= not vme_irq_n_o;
inst_vme_core : xvme64x_core
inst_vme_core : entity work.xvme64x_core
generic map (
g_CLOCK_PERIOD => 8,
g_DECODE_AM => True,
g_USER_CSR_EXT => False,
g_WB_GRANULARITY => BYTE,
g_MANUFACTURER_ID => c_CERN_ID,
g_BOARD_ID => c_SVEC_ID,
......@@ -346,17 +265,6 @@ begin -- architecture top
vme_addr_dir_o <= vme_addr_dir_int;
vme_data_dir_o <= vme_data_dir_int;
-- tri-state Carrier EEPROM
-- carrier_sda_b <= 'Z';
-- carrier_scl_b <= 'Z';
-- Tristates for SFP EEPROM
-- sfp_mod_def1_b <= 'Z';
-- sfp_mod_def2_b <= 'Z';
-- tri-state onewire access
-- onewire_b <= 'Z';
------------------------------------------------------------------------------
-- Carrier front panel LEDs and LEMOs
------------------------------------------------------------------------------
......
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