Commit 1632a555 authored by Federico Vaga's avatar Federico Vaga

Merge remote-tracking branch 'origin/proposed_master' into develop

parents 4df4d362 3da89c5c
......@@ -380,7 +380,6 @@ architecture top of svec_template_wr is
signal vme_ga : std_logic_vector(5 downto 0);
signal vme_berr_n : std_logic;
signal vme_irq_n : std_logic_vector(7 downto 1);
signal irq_to_vme : std_logic;
-- The wishbone bus to the carrier part.
signal carrier_wb_out : t_wishbone_slave_out;
......@@ -502,7 +501,7 @@ begin -- architecture top
vme_o.addr_oe_n => vme_addr_oe_n_o,
wb_o => vme_wb_out,
wb_i => vme_wb_in,
int_i => irq_to_vme);
int_i => irq_master);
vme_ga <= vme_gap_i & vme_ga_i;
vme_berr_o <= not vme_berr_n;
......@@ -516,7 +515,7 @@ begin -- architecture top
vme_addr_dir_o <= vme_addr_dir_int;
vme_data_dir_o <= vme_data_dir_int;
-- Mini-crossbar from gennum to carrier and application bus.
-- Mini-crossbar from vme to carrier and application bus.
inst_split: entity work.xwb_split
generic map (
g_mask => x"ffff_e000"
......@@ -538,7 +537,7 @@ begin -- architecture top
clk_i => clk_sys_62m5,
wb_cyc_i => carrier_wb_in.cyc,
wb_stb_i => carrier_wb_in.stb,
wb_adr_i => carrier_wb_in.adr (12 downto 2), -- Bytes address from gennum
wb_adr_i => carrier_wb_in.adr (12 downto 2), -- Bytes address from vme64x core
wb_sel_i => carrier_wb_in.sel,
wb_we_i => carrier_wb_in.we,
wb_dat_i => carrier_wb_in.dat,
......@@ -613,10 +612,10 @@ begin -- architecture top
if rising_edge(clk_sys_62m5) then
case metadata_addr is
when x"0" =>
-- Vendor ID
-- Vendor ID
metadata_data <= x"000010dc";
when x"1" =>
-- Device ID
-- Device ID
metadata_data <= x"53564543";
when x"2" =>
-- Version
......
......@@ -23,7 +23,8 @@ files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/golden_wr",
],
"../../syn/common",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
......
......@@ -134,8 +134,6 @@ entity svec_golden_wr is
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
pll20dac_din_o : out std_logic;
pll20dac_sclk_o : out std_logic;
pll20dac_sync_n_o : out std_logic;
......@@ -190,10 +188,10 @@ entity svec_golden_wr is
fp_led_column_o : out std_logic_vector(3 downto 0);
-- GPIO
fp_gpio1_o : out std_logic; -- PPS output
fp_gpio2_o : out std_logic; -- not used
fp_gpio3_o : out std_logic; -- not used
fp_gpio4_o : out std_logic; -- not used
fp_gpio1_b : out std_logic; -- PPS output
fp_gpio2_b : out std_logic; -- not used
fp_gpio3_b : out std_logic; -- not used
fp_gpio4_b : out std_logic; -- not used
fp_term_en_o : out std_logic_vector(4 downto 1);
fp_gpio1_a2b_o : out std_logic;
fp_gpio2_a2b_o : out std_logic;
......@@ -284,8 +282,6 @@ begin
uart_txd_o => uart_txd_o,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o,
......@@ -441,10 +437,10 @@ begin
led_state(15 downto 14) <= c_led_red_green when wr_led_act = '1' else c_led_off;
-- Front panel IO configuration
fp_gpio1_o <= pps_p;
fp_gpio2_o <= '0';
fp_gpio3_o <= '0';
fp_gpio4_o <= '0';
fp_gpio1_b <= pps_p;
fp_gpio2_b <= '0';
fp_gpio3_b <= '0';
fp_gpio4_b <= '0';
fp_term_en_o <= (others => '0');
fp_gpio1_a2b_o <= '1';
fp_gpio2_a2b_o <= '1';
......
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