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  • master default protected
    190e95de · Merge branch '15-release_v3.0.0' into 'master' · Dec 05, 2022
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  • adam-tdc
    1be4f060 · hdl/rtl/svec_base_regs: fix svec_base_regs.cheby for rest map generation · Jun 22, 2022
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  • tom-svec7
    9149d19b · testbench: simple TB for the SFPGA+AFPGA bridged mode operation · Sep 06, 2021
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  • feature/bootloader-retry
    cb16feb6 · sw: replace loader retry with a 1ms timeout · Jul 08, 2021
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  • feature/svec-dma
    708beb98 · svec-dma.c: remove traces · Mar 10, 2021
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  • tgingold-testcard
    9ab7e2c6 · vme16_test: use pipelined wb, fix memmap comment · Feb 08, 2021
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  • tgingold-tester_wr
    bc5bb9fa · tester_wr: add fpga-dev-id · Apr 09, 2020
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  • feature/svec-dbg-irq-gen
    9a2fa9b9 · sw:drv: add basic structure for debugging driver · Apr 07, 2020
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  • tom-svec7-test
    bd991588 · syn: svec7 XDC & synthesis files · Dec 12, 2019
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  • proposed_master protected
    72f8d1dd · svec_vme16: add syn project, modify design. · Nov 14, 2019
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  • tom-ddmtd-clock-output
    41415b81 · svec_base_wr: added DDMTD clock output · Oct 15, 2019
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  • tom-ctrv-v5-bootloader
    c6cfb425 · bootloader: make sure flash is always visible for the SFPGA · Feb 23, 2017
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