csr

Control and status registers

Wishbone slave for control and status registers

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Carrier informations
3.2. Bitstream type
3.3. Bitstream date
3.4. Status
3.5. Control

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Carrier informations csr_carrier CARRIER
0x1 REG Bitstream type csr_bitstream_type BITSTREAM_TYPE
0x2 REG Bitstream date csr_bitstream_date BITSTREAM_DATE
0x3 REG Status csr_stat STAT
0x4 REG Control csr_ctrl CTRL

2. HDL symbol

→ rst_n_i Carrier informations:
→ wb_clk_i csr_carrier_pcb_rev_i[4:0] ⇐
⇒ wb_addr_i[2:0] csr_carrier_reserved_i[10:0] ⇐
⇒ wb_data_i[31:0] csr_carrier_type_i[15:0] ⇐
⇐ wb_data_o[31:0]  
→ wb_cyc_i Bitstream type:
⇒ wb_sel_i[3:0] csr_bitstream_type_i[31:0] ⇐
→ wb_stb_i  
→ wb_we_i Bitstream date:
← wb_ack_o csr_bitstream_date_i[31:0] ⇐
 
Status:
csr_stat_fmc1_pres_i ←
csr_stat_fmc2_pres_i ←
csr_stat_sys_pll_lck_i ←
csr_stat_ddr3_bank4_cal_done_i ←
csr_stat_ddr3_bank5_cal_done_i ←
csr_stat_gpio_in_i[3:0] ⇐
csr_stat_reserved_i[22:0] ⇐
 
Control:
csr_ctrl_fp_leds_auto_o →
csr_ctrl_fp_leds_o[15:0] ⇒
csr_ctrl_fp_led_int_o[6:0] ⇒
csr_ctrl_gpio_1_dir_o →
csr_ctrl_gpio_2_dir_o →
csr_ctrl_gpio_34_dir_o →
csr_ctrl_gpio_out_o[3:0] ⇒

3. Register description

3.1. Carrier informations

HW prefix: csr_carrier
HW address: 0x0
C prefix: CARRIER
C offset: 0x0
31 30 29 28 27 26 25 24
TYPE[15:8]
23 22 21 20 19 18 17 16
TYPE[7:0]
15 14 13 12 11 10 9 8
RESERVED[10:3]
7 6 5 4 3 2 1 0
RESERVED[2:0] PCB_REV[4:0]

3.2. Bitstream type

HW prefix: csr_bitstream_type
HW address: 0x1
C prefix: BITSTREAM_TYPE
C offset: 0x4
31 30 29 28 27 26 25 24
BITSTREAM_TYPE[31:24]
23 22 21 20 19 18 17 16
BITSTREAM_TYPE[23:16]
15 14 13 12 11 10 9 8
BITSTREAM_TYPE[15:8]
7 6 5 4 3 2 1 0
BITSTREAM_TYPE[7:0]

3.3. Bitstream date

HW prefix: csr_bitstream_date
HW address: 0x2
C prefix: BITSTREAM_DATE
C offset: 0x8
31 30 29 28 27 26 25 24
BITSTREAM_DATE[31:24]
23 22 21 20 19 18 17 16
BITSTREAM_DATE[23:16]
15 14 13 12 11 10 9 8
BITSTREAM_DATE[15:8]
7 6 5 4 3 2 1 0
BITSTREAM_DATE[7:0]

3.4. Status

HW prefix: csr_stat
HW address: 0x3
C prefix: STAT
C offset: 0xc
31 30 29 28 27 26 25 24
RESERVED[22:15]
23 22 21 20 19 18 17 16
RESERVED[14:7]
15 14 13 12 11 10 9 8
RESERVED[6:0] GPIO_IN[3:3]
7 6 5 4 3 2 1 0
GPIO_IN[2:0] DDR3_BANK5_CAL_DONE DDR3_BANK4_CAL_DONE SYS_PLL_LCK FMC2_PRES FMC1_PRES

3.5. Control

HW prefix: csr_ctrl
HW address: 0x4
C prefix: CTRL
C offset: 0x10
31 30 29 28 27 26 25 24
- GPIO_OUT[3:0] GPIO_34_DIR GPIO_2_DIR GPIO_1_DIR
23 22 21 20 19 18 17 16
FP_LED_INT[6:0] FP_LEDS[15:15]
15 14 13 12 11 10 9 8
FP_LEDS[14:7]
7 6 5 4 3 2 1 0
FP_LEDS[6:0] FP_LEDS_AUTO