PXI express FMC Carrier Board (SPEXI)
Project description
The PXI express FMC Carrier Board (SPEXI) is the PXI express version of the SPEC board. It is an FMC carrier that can hold one FMC card and an SFP connector. On the PXI express side it has a 4-lane interface, while the FMC mezzanine slot uses a low-pin count connector. This board is optimised for cost and will be usable with most of the FMC cards designed within CERN’s OHR project (e.g. ADC cards, Fine Delay).
Spexi means "I observe, watch, look at." in Latin.
Main Features
* 4-lane PCIe (Gennum GN4124)
* FMC slot with low pin count (LPC) connector
o Vadj fixed to 2.5V
o No dedicated clock signals from Carrier to FMC (only available on HPC
pins)
o LPC cheaper than HPC and also easier to mount
o FMC connectivity: all 34 differential pairs connected, 1 GTP
transceiver with clock, 2 clock pairs, JTAG
* 1 Xilinx Spartan6 FPGA (XC6SLX45T) or equivalent
* Simple clocking resources
o 1 10-280 MHz I2C Programmable XO Oscillator (Silicon Labs Si570)
o 1 25 MHz TCXO controlled by a DAC with SPI interface (AD5662)
o 1 20 MHz VCXO controlled by a DAC with SPI interface (AD5662)
o 1 low-jitter frequency synthesizer (TI CDCM61004, fixed configuration,
Fout=125MHz)
* On board memory
o A 2Gbit DDR3
o 1 SPI 32Mbit flash PROM for multiboot FPGA powerup configuration,
storage of the FPGA firmware or of critical data
* Front panel containing
o 1 Small Formfactor Pluggable (SFP) cage for fibre-optic transceiver
(WhiteRabbit support)
o Programmable LED
o FMC front panel
* Internal connectors
o 1 JTAG header for Xilinx programming during debugging
o 1 mini USB AB (USB-UART bridge)
* FPGA configuration. The FPGA can optionally be programmed from:
o GN4124 SPRIO interface (loaded by software driver at startup)
o JTAG header
o SPI 32Mbit flash PROM
o selectable by GN4124 GPIO. Default option would be loading via the SPI
flash PROM (stand-alone applications).
* Debugging features
o mini USB connector
o 4 LEDs
o 2 buttons
* Optimised for cost
PXIe specific features
* PXI express form factor, 3U high, single slot
* Clock and synchronisation back plane signals
PXI clock and synchronisation signals | PXI express clock and synchronisation signals |
PXI_TRIG[0:7] | PXIe_DSTARA |
PXI_CLK10 | PXIe_DSTARB |
PXI_STAR | PXIe_DSTARC |
PXI_LBL6 | PXIe_CLK100 |
PXI_LBR6 | PXIe_SYNC100 |
Project information
- Official production documentation:
- Design Information
- Software
- Users
Releases
Contacts
Commercial producers
- Please contact INCAA Computers, Netherlands, the company that is currently designing this board.
General question about project
- Erik van der Bij - CERN
- Adriaan Rijllart - CERN - project initiator
Status
Date | Event |
06-04-2011 | First ideas for project. |
17-01-2012 | Price Enquiry sent out for design by industry based on SPEC board. |
12-03-2012 | Order for design and two pre-series boards placed with INCAA. Delivery by 12-07-2012. |
16-05-2012 | Schematics being made. |
29-05-2012 | Removed SATA connectors and stand-alone possibility from specification. |
17-08-2012 | V0 Schematics and PCB uploaded and available for review |
30-08-2012 | First review V0 Review20120830. |
04-10-2012 | Second schematics review V0. |
19-11-2012 | V0-2 ready for review. |
Erik van der Bij, Adriaan Rijllart - 30 November 2012