This wiki page describes different discussion points for the
specification of the
Aim and Use cases
NIKHEF/JRP, CERN: as high-precision PCIe and stand-alone White Rabbit design
* Aim: White Rabbit node with target frequency instability of 1e-13
over 100 sec.
* Users will be first: research institutes and metrology institutes
with the aim to disseminate UTC from metrology partners to European
research institutes and industry partners. Later: high performance
users, telecom, ....
All users profit from an inherent high performance, relatively
cheap (?), design without the bother of buying an expensive stable
external oscillator that the metrology users need.
* Other possible user for 1 GSPS ADC cards requiring HPC FMC? Needs to
be worked out as fast ADCs nowadays use many serial links and have no
* Quantity: 100 in 5 years for metrology and research needing high
optimise for performance
CERN: as SPEC replacement
* Aim: smooth replacement of existing SPEC that is a cheap FMC carrier
with WR support.
The existing SPEC with WRS are the two flagship OH projects and the
SPEC7 therefore may not fail as project.
* Used by
and other FMC mezzanines.
Many current SPEC
users have their
in-house designed FMC mezzanines. Should provide a compatible
micro USB-OTG (so it can act as host and as slave). But then we
should rename the card to SPUEC or SUPEC (U for USB). Perhaps this
is a crazy idea, but it is nice to think that users can plug'n'play
the SPUEC/SUPEC on their laptop :) (FV)
The current mini-USB can serve two UARTs over the same single
mini-USB connector if we use a CP2105 - Dual UART
Quite handy if you have a WRPC gui and other logic in your FPGA.
10 layer PCB so that layout can be optimised for low-jitter
High-speed connector for PPS in/out, 10MHz in, tx-abscal, rx-abscal,
refclock. 6 signals to be transferred in a differential way Samtec
Bulls-Eye connector (just a land pattern for 22 signals on the
We need high performance timing-IO signals (including absolute
calibration signals) on (accessible) connectors. The current DIO is
really bad for timing. We (Guido) should look into this. A possible
candidate is a Samtec Bulls-Eye which is just a land pattern on your
PCB. But we should study this since a Bulls-Eye is the perfect phase
plane reference but the phase plane will not be very accessible from
the outside world (i.e. on the PCI bracket).
Timing signals should be re-clocked with high speed FFs outside the
FPGA. I remember that this was an issue that you CERN guys also
We need to think of some digital interface (including connectors) to
close an external PLL loop using an external high performance
oscillator. Ideas are still vague at this moment but the interface
as such should already be on the list.
Keep same SATA connectors as on SPEC.
Is a connector specifically for internal use (i.e., not
Planned to be used on SPEC for daisy-chaining triggers between
SPECs with FMC-ADCs with modified gateware.
May be used as well for digital interface for external PLL loop