SPEC7 Feature alternatives
Cost of Alternatives
Existing SPEC: 180 Euro component cost (without PCB and front-panel) when bought in large quantities (several hundreds in one time).
- Replacing Gennum: (57 Euro) and Spartan (40 Euro) by
XC7K70T-2FBG676C negotiated down to 90 Euro makes component cost
similar to existing SPEC.
- Note that list price K70T is 180 Euro. With this price, the SPEC7 would have already a 50% higher cost than the SPEC.
Alternative options:
- XC7K160T-2FBG676C (~260 Euro) (+80 Euro)
- Vadj adjustable (~+5 Euro)
- Larger PCB for extra connectors (+10 Euro)
- High Pin Count FMC connector (+6Euro)
- Connor-Winfield DOT050 VCTCXO (DOT050V-020.0M) (+20 Euro)
- 12-layer PCB (if HPC) (+30 Euro)
Total: with all options, 150 Euro extra cost, total cost price 330 Euro. This is an 80% price increase.
Alternative Xilinx Zynq series with ARM processor integrated:
- XC7Z030-2FBG676E (~285 Euro) (-2=faster, Extended temp range only, not available in commercial temp range)
- XC7Z030-1FBG676C (~206 Euro) (-1= slower, commercial temp range)
SPEC7 Feature Alternatives
- 4-lane PCIe ****
- 1x Xilinx handling PCIe interface and user gateware
- Xilinx Kintex-7: XC7K70T in FBG676 package (XC7K70T-2FBG676C)
(~180 Euro)
- Alternative: XC7K160T-2FBG676C (+80 Euro)
- Alternative: XC7Z030-2FBG676E (+105 Euro), -1 version somewhat cheaper.
- Xilinx Kintex-7: XC7K70T in FBG676 package (XC7K70T-2FBG676C)
(~180 Euro)
- FMC slot with low pin count (LPC) connector
- Vadj fixed to 2.5V
- Alternative Vadj adjustable (~+5 Euro)
- FMC connectivity: all 34 differential pairs connected, 1 GTP transceiver with clock, 2 clock pairs, JTAG, I2C
-
Alternative: HPC (+6Euro)
- No additional GTX lines. Not all signals populated. No extra GTP lines, so not useful for modern JESD204 Serial Interface ADC.
- Vadj fixed to 2.5V
- Clocking resources
- 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100 MHz (Silicon Labs Si570, freely usable)
- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
- 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662,
used by White Rabbit PTP
core)
(~2.50 Euro)
- Alternative: Connor-Winfield DOT050 VCTCXO (DOT050V-020.0M) (+20 Euro)
- Same as used on WRS Low-jitter daughterboard, (~22 Euro)
- 1x low-jitter frequency synthesizer (TI CDCM61004, fixed configuration, Fout=125 MHz, used by White Rabbit PTP core)
- On board memory
- 1x 2Gbit (256 MByte) DDR3 (MT41J128M16HA-15E)
- 1x SPI 32Mbit flash PROM for multiboot FPGA powerup configuration, storage of the FPGA firmware or of critical data (M25P32-VMF6P - EOL)
- Miscellaneous
- on-board thermometer IC (DS18B20U+)
- unique 64-bit identifier (DS18B20U+)
- Front panel containing
- 1x Small Formfactor Pluggable (SFP) cage for fibre-optic transceiver (WhiteRabbit support). 1.25 and 2.5 Gbps.
- Programmable Red and Green LEDs
- FMC front panel
- Internal connectors
- 1x JTAG header for Xilinx programming during debugging
- 2x SATA connector
- 1x mini USB AB (USB-UART bridge)
- *Alternative: High-speed connector for PPS in/out, 10MHz in,
tx-abscal, rx-abscal, refclock. 6 signals to be transferred in a
differential way Samtec Bulls-Eye connector (just a land pattern
for 22 signals on the
PCB
- Needs larger PCB (+10 Euro)
- Are all signals available without any additional cost?
- FPGA configuration. The FPGA can optionally be programmed from:
- JTAG header
- SPI 32Mbit flash PROM
- Stand-alone features
- External 12V power supply connector
- mini USB connector
- 4 LEDs
- 2 buttons
- Power consumption: 5-12 Watt, depending on application
- Optimised for cost
- 8-layer PCB
- was 6-layer on SPEC (PCB cost 13.7% of final sales price)
- Alternative: 12-layer PCB (if HPC) (+30 Euro)
- 8-layer PCB
- Optional cooling fan for the mezzanine.
Erik van der Bij - 29 January 2018