Simple PCIe FMC carrier 7 (SPEC7)
The FMC PCIe Carrier called SPEC7 is an FMC carrier that can hold one
FMC card and an SFP connector.
This board uses a Xilinx Zynq FPGA with Dual-Core ARM processor integrated and is optimised for low jitter and cost and is usable with most of the FMC cards designed within the OHR project (e.g. ADC cards, Fine Delay).
The design is done in a collaboration between NIKHEF (NL) and CERN as both need a card with a similar functionality.
The SPEC7 is the follow-up of the
SPEC of which the design
started in 2010 and for which certain components are obsolete.
Boards with a very similar architecture are available for the VME bus (SVEC - Simple VME FMC Carrier) and for the PXI Express bus (SPEXI - Simple PXI express FMC Carrier Board).
Other FMC projects and the FMC standard are described in FMC Projects.
The SPEC7. It will be a follow-up of the SPEC board. Click the picture for a detailed component side view.
- 2-lane PCIe Gen2
- Same 1 GByte/s total speed as 4-lane PCIe Gen1 on SPEC. Bridge integrated in FPGA
- Xilinx Zynq FPGA with Dual-Core ARM processor integrated
XC7Z035-1FBG676C (-1= slowest, commercial temp range, fast enough for most
- 8 GTX Tranceivers (2 used for PCIe, 1 for SFP, 1 external accessible, 4 for FMC)
- 4 GTX Reference Clocks (1 for PCIe, 1 for WR Clock, 1 for FMC, 1 external accessible)
- FBG676 6.6 Gb/s (-1 speedgrade), FFG676 10.3125 Gb/s (-2 speedgrade) or 12.5 Gb/s (-3 speedgrade) GTX transceivers (DS191, Table 91)
- Possibility to mount XC7Z045-1FBG676C, but not XC7Z030-1FBG676C (see Issue #22 (closed))
- XC7Z035-1FBG676C (-1= slowest, commercial temp range, fast enough for most applications)
- FMC slot with high pin count (HPC) connector
- Fully populated LA bank
- All 34 differential pairs connected, 2 clock pairs, I2C (as on SPEC)
- JTAG accessible from the FPGA. JTAG switches automatically to the download cable when it is plugged.
- Z035 and Z045 support 4 GTX transceivers DP[3:0]_M2C/C2M
- Vadj fixed 2.5V (HR bank of the ZYNQ only allows LVDS_25 at VCCO 2V5, see UG471 table 1-43)
- Fully populated LA bank
- Clocking resources
- 1x Fixed frequency 33.33 MHz oscillator for Application Processor Unit (APU)
- 1x 10-280 MHz VCXO controlled by I2C and a DAC with SPI interface. Starts up at 125 MHz (Silicon Labs Si570/Si571, freely usable)
- 1x 125.000 MHz VCXO controlled by a DAC with SPI interface (used by White Rabbit PTP core) (Abracon ABLANO or Crystek CVPD-922 model)
- 1x 124.992 MHz VCXO controlled by a DAC with SPI interface (used by White Rabbit PTP core) (Abracon ABLANO or Crystek CVPD-922 model)
- Low jitter external 10MHz via LTC6950 (supporting mode Grand Master & AbsCal)
- 10MHz TCXO for IEEE1588 v2.1 compliance (see J5.6.1) in Free-running Master mode.
- On board memory
- 1x 8 Gbit (1 GByte) DDR3 connected to the 32-bit wide Memory Interface (main use for the APU)
- 1x 8 Gbit (1 GByte) DDR3 connected to the programmable logic (32 bit wide)
- 2x QSPI 256 Mbit flash PROM for multiboot FPGA powerup configuration, storage of the FPGA firmware. Note that 8-bit Dual Quad SPI is needed to meet the 100 ms PCIe endpoint requirement w.r.t. configuration time.
- 64K (8K x 8-bit) I2C Serial EEPROM (24AA64T-I/MC) for storing serial number, calibration parameters and other critical data such as the MAC address of the card
- 2x 2K (128 x 8-bit) I2C Serial EEPROM (24AA025E48) which provides EUI-48
- 1 for APU MAC address
- 1 for WR MAC address
- MicroSD slot for flash memory for storing programs
- Thermometer (XADC) and semi-unique ID (DNA_PORTE2) provided by the FPGA
- Front panel containing
- 1x Small Formfactor Pluggable+ (SFP+) cage for fibre-optic transceiver (WhiteRabbit support). 1.25, and 2.5 Gbps
- Programmable Red and Green LEDs
- FMC front panel
- Internal connectors
- 1x JTAG header for Xilinx programming during debugging
- 1x mini USB Type B connector
- Can serve two UARTs over the same single mini-USB connector
with CP2105 - Dual UART bridge IC
- One to UART interface of the ARM
- One to user logic (e.g., PTP core)
- Can serve two UARTs over the same single mini-USB connector with CP2105 - Dual UART bridge IC
- 1x USB Type A connector connected to USB 2.0 port of the ARM
- Ethernet RJ45 connector, magnetics and MicroChip KSZ9031RNX, 10/100/1000 Mbps PHY (interface to ARM GigE)
- Samtec Bulls-Eye connector (BDRA: 20 signals on the PCB, 1.3 x 5.0 = 6.5 cm2 land pattern, user mountable connector)
- ESD protection on all signals
- 11 differential signals:
- 125 MHz reference clock in (Z035/Z045 only)
- 125 MHz reference clock out
- 1x tx-abscal
- 10 MHz reference clock in/out
- PPS in/out
- 1x GTX Tx/Rx (using 125 MHz reference clock; optional other reference clock when using Z035/Z045)
- 1x spare
- 124.992 MHZ DMTD clock (only for debugging purposes)
- 1 single ended signal:
- PPS in
- 2x connector for optional cooling fans
- FPGA configuration. The FPGA can optionally be programmed from:
- JTAG header
- Dual QSPI 256 Mbit FLASH PROM
- User FPGA logic: via PCIe or ARM (i.e. using [PS PCAP / ICA](see chapter 6.1.8 Zynq-7000 SoC Technical Reference Manual)
- Stand-alone features
- External 12V 150W-ATX power supply connector
- USB Type A connector
- mini USB Type B connector
- 10/100/1000 Mbps copper Ethernet RJ45
- SFP+ cage for fibre-optic transceiver(WhiteRabbit support)
- 7x LEDs (2x front pannel, 4x on PCB, 1x PCI SMB-bus)
- 5x buttons
- 1 PS_POR connected to reset controller
- 1 PS_SRTS_B
- 1 PL system reset
- 1 general purpose
- 1 PROGram button for FPGA
- Power consumption: 10-35 Watt, depending on application
- 14-layer PCB
- Optional cooling fans
- for the mezzanine
- for the FPGA
- Official production documentation
- Schematics (Note: Design created with Mentor Graphics using a Xpedition).
- Preliminary SPEC7 documentation
- Manufacturing files 11300.01.05.2_SPEC7_v2.zip (Note: PCB Design created with Mentor Graphics using a Xpedition License)
- PCB Design files spec7_v2.020200518093142.zip (Note: PCB Design created with Mentor Graphics using a Xpedition License)
- Design Specification
- Specification gathering discussion - a list of wish items ...
- Feature Alternatives - ... boiling down to a few alternatives ...
- Design specification May 2018 - Design specification August 2019... to a precise specification that allows the design to start. A cleaned-up version can be found on this very page at Main Features.
- Component Selection - ... list of selected components.
- Work partially funded by the EU EMPIR WRITE project
- Frequently Asked Questions
- Test, Measurements, Reports and Older Versions of SPEC7
- High Precision Oscillator (HPSEC), optional external device
- Once designed and debugged, the board will be commercially available.
General questions about project
- Erik van der Bij - CERN
- Peter Jansweijer, Pascal Bos, Guido Visser - NIKHEF
|10-01-2018||Start working on project. Collecting main specifications.|
|12-01-2018||Main specifications collected. Discussion points documented.|
|29-01-2018||Specifications taking shape: Specification gathering discussion - a list of wish items &
Feature Alternatives - boiling down to a few alternatives
|07-03-2018||Specification gathering discussion and Feature Alternatives stabelised.|
|11-05-2018||Specification reviewed by Sundance.|
Feature Alternatives clarified at 2-day visit from NIKHEF and Tsinghua University at CERN
to result in the Design specification.
Design specification reviewed and used in Main Features.
NIKHEF will start designing in June. First prototypes expected by December 2018.
|10-07-2018||NIKHEF will first design a test board with only XC7Z035 and oscillators (no DDR, no DC/DC)
to measure lowest phase noise possible.
|25-07-2018||Planning: Dec-18: schematics ready for review. Feb-19: schematics ready, layout start (4 weeks).
Production (8 weeks): Prototype available by end April 2019.
|17-09-2018||Added component selection list.|
|30-11-2018||Zynq Phase Noise Test Board received.|
|14-12-2018||First draft of schematics made. Not yet ready for review.|
|30-01-2019||Planned to have schematics ready for review on 15-Feb-19. Layout should start beginning of March.|
|14-02-2019||Schematics ready to be reviewed.|
|14-03-2019||Schematics reviewed by Sundance and CERN.|
|29-03-2019||Updated specifications after schematics review.|
|18-04-2019||Schematics updated after schematics review. Layout can start.|
|19-08-2019||Planning: 2 boards production & assembly ready: Nov.2019. 10 boards production & assembly ready: Jan.2020|
|18-11-2019||First two prototypes arrived.|
|10-12-2019||Testing revealed a couple of minor issues and one major issue. A 2nd version PCB is needed.|
|31-01-2020||Layout of V2 finalized.|
|07-04-2020||First batch of four V2 boards expected by end May. If OK, batch of 8 ready in July.|
|15-05-2020||First batch of four V2 boards tested okay, green light for the next batch of 8.|
|25-06-2020||Second batch of eight V2 boards received.|
|01-07-2020||Second batch of eight V2 boards tested okay.|
|18-09-2020||Update SPEC7 documentation.|
10 December 2020