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SPEC7

Designspecification

Last edited by Erik van der Bij
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Design Specification

SPEC7 Design Specification

This specification is based on Feature Alternatives with updates made at the end of May 2018 in bold.

SPEC7 Features

  • 2-lane PCIe Gen2
    • Same 1 GByte/s total speed as 4-lane PCIe Gen1 on SPEC. Bridge integrated in FPGA
  • Xilinx Zynq FPGA with ARM processor integrated
    • XC7Z030-1FBG676C (~206 Euro) (-1= slowest, commercial temp range, fast enough for most applications?)
      • 4 GTX receivers (2 used for PCIe, 1 for SFP, 1 for FMC - same as on SPEC)
    • Possibility to mount Z035: XC7Z035-1FBG676C or XC7Z045-1FBG676C
      • 8 GTX receivers (2 used for PCIe, 1 for SFP, 5 for FMC)
  • FMC slot with high pin count (HPC) connector
    • Vadj programmable at 1.8V and 2.5V
      • 2.5V can only be used with a LPC FMC mezzanine: only the LPC pins (LA bank) are 2.5V tolerant.
    • Fully populated LA bank
      • All 34 differential pairs connected, 1 GTP transceiver with clock, 2 clock pairs, JTAG, I2C (as on SPEC)
    • Limited, partial connectivity of HPC part, 1.8V tolerant only
      • xx signals on HA bank
      • HA bank only 1.8V tolerant (Vadj set to 1.8V)
      • only when Xilinx Z035 or Z040 is mounted, the DP1_M2C/C2M and DP2_M2C/2CM are connected to two GTX transceivers
  • Clocking resources
    • 1x Fixed frequency oscillator for Application processor unit (APU) (frequency?)
    • 1x 10-280 MHz VCXO controlled by I2C and a DAC with SPI interface. Starts up at 100 MHz (Silicon Labs Si571, freely usable)
    • 1x 125 MHz TCXO controlled by a DAC with SPI interface (used by White Rabbit PTP core) (Crystek CVPD-922 model)
    • 1x 124.992 MHz VCXO controlled by a DAC with SPI interface (used by White Rabbit PTP core) (Crystek CVPD-922 model)
  • On board memory
    • 1x 8 Gbit (1 GByte) DDR3 IC connected to the Memory Interface (main use for the APU)
      • a 4 GByte SO-DIMM module cannot be used: has 64-bit interface, while the FGPA can only handle 32-bits and1 GByte max)
    • 1x 8 Gbit (1 GByte) DDR3 IC connected to the programmable logic
      • for bandwidth reasons
      • Possibly a second 8 Gbit DDR3 IC to prevent the DDR3 problem of the latency and turnaround from READ to WRITE – two banks solve the problem.
    • 1x SPI xx Mbit flash PROM for multiboot FPGA powerup configuration, storage of the FPGA firmware
    • 64K (8K x 8-bit) I2C Serial EEPROM (24AA64T-I/MC) for storing serial number, calibration parameters and other critical data such as the MAC address of the card
    • 64 MB static memory (needed for booting?)
    • MicroSD slot for flash memory for storing programs
  • Miscellaneous
    • On-board thermometer IC (DS18B20U+)
    • Unique 64-bit identifier (DS18B20U+)
  • Front panel containing
    • 1x Small Formfactor Pluggable+ (SFP+) cage for fibre-optic transceiver (WhiteRabbit support). 1.25, and 2.5 Gbps
    • Programmable Red and Green LEDs
    • FMC front panel
  • Internal connectors
    • 1x JTAG header for Xilinx programming during debugging
    • 2x 14-pin header connector connected to GPIO, with ESD protection
    • 1x USB-C connector
      • Can serve two UARTs over the same single mini-USB connector with CP2105 - Dual UART bridge IC
        • One to UART interface of the ARM, one to user logic (e.g., PTP core)
    • 1x USB-C connector connected to USB port of the ARM
    • Samtec Bulls-Eye connector (22 signals on the PCB, 6 cm2 land pattern, user mountable connector)
      • For PPS in/out, 10MHz in, tx-abscal, rx-abscal, refclock. 5 signals to be transferred in a differential way
      • ESD protection on all signals
    • Ethernet RJ45 connector + magnetics and PHY (interface to ARM GigE)
  • 1x connector for optional cooling fan
  • FPGA configuration. The FPGA can optionally be programmed from:
  • Stand-alone features
    • External 12V power supply connector
    • USB-C connector
    • Ethernet
    • 4x LEDs
    • 2x buttons
      • 1 connected to reset controller
      • 1 general purpose
  • Power consumption: 5-12 Watt, depending on application
  • Optimised for cost
    • 8-layer PCB
  • Optional cooling fan for the mezzanine

30 May 2018