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SPEC7
Commits
f8a0fe41
Commit
f8a0fe41
authored
Feb 23, 2022
by
Pascal Bos
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Changed design to v2 with hpsec
parent
dfc0d7aa
Pipeline
#3249
failed with stage
in 2 minutes and 6 seconds
Changes
3
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3 changed files
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7 additions
and
7 deletions
+7
-7
proj_properties.tcl
hdl/syn/spec7_ref_design/proj_properties.tcl
+3
-3
spec7_wr_hpsec_top_v2.xdc
hdl/top/spec7_ref_design/spec7_wr_hpsec_top_v2.xdc
+2
-2
spec7_wr_ref_top_v2.xdc
hdl/top/spec7_ref_design/spec7_wr_ref_top_v2.xdc
+2
-2
No files found.
hdl/syn/spec7_ref_design/proj_properties.tcl
View file @
f8a0fe41
...
...
@@ -11,10 +11,10 @@
set
version
""
# Reference Design (using fmc-dio-5chttla => https://ohwr.org/project/fmc-dio-5chttla/wikis/home
)
# HPSEC Design (using Bulls-Eye connector
)
set
spec7_design spec7_ref_top
#
set spec7_design spec7_hpsec_top
#
set spec7_design spec7_ref_top
set
spec7_design spec7_hpsec_top
# Uncomment the line below for older SPEC7v2
#
set version "_v2"
set
version
"_v2"
# ====================================================
# ====================================================
...
...
hdl/top/spec7_ref_design/spec7_wr_hpsec_top_v2.xdc
View file @
f8a0fe41
...
...
@@ -624,11 +624,11 @@ set_property IOSTANDARD LVCMOS25 [get_ports fmc_la31_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la31_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 3
set_property PACKAGE_PIN AB12 [get_ports fmc_la32_p]
set_property IOSTANDARD LV
CMOS
25 [get_ports fmc_la32_p]
set_property IOSTANDARD LV
DS_
25 [get_ports fmc_la32_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la32_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 4
set_property PACKAGE_PIN AC11 [get_ports fmc_la32_n]
set_property IOSTANDARD LV
CMOS
25 [get_ports fmc_la32_n]
set_property IOSTANDARD LV
DS_
25 [get_ports fmc_la32_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la32_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 5
set_property PACKAGE_PIN AE10 [get_ports fmc_la33_p]
...
...
hdl/top/spec7_ref_design/spec7_wr_ref_top_v2.xdc
View file @
f8a0fe41
...
...
@@ -619,11 +619,11 @@ set_property IOSTANDARD LVCMOS25 [get_ports fmc_la31_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la31_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 3
set_property PACKAGE_PIN AB12 [get_ports fmc_la32_p]
set_property IOSTANDARD LV
CMOS
25 [get_ports fmc_la32_p]
set_property IOSTANDARD LV
DS_
25 [get_ports fmc_la32_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la32_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 4
set_property PACKAGE_PIN AC11 [get_ports fmc_la32_n]
set_property IOSTANDARD LV
CMOS
25 [get_ports fmc_la32_n]
set_property IOSTANDARD LV
DS_
25 [get_ports fmc_la32_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la32_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 5
set_property PACKAGE_PIN AE10 [get_ports fmc_la33_p]
...
...
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