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SPEC7
Commit eea1d0c2 authored by Peter Jansweijer's avatar Peter Jansweijer
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Don't read bmm file into Vivado project (to avoid error).

parent ca3fae43
Pipeline #3367 failed with stage
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    hdl/top/spec7_ref_design/spec7_wr_hpsec_top.xdc
    View file @ eea1d0c2
    ......@@ -59,9 +59,6 @@ set_multicycle_path 1 -hold -from [get_clocks clk_125m_gtx_odiv2] -to [get_clock
    set_multicycle_path 3 -setup -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_125m_gtx_odiv2]
    set_multicycle_path 2 -hold -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_125m_gtx_odiv2]
    # Set BMM_INFO_DESIGN property to avoid ERROR during "Write Bitstream"
    set_property BMM_INFO_DESIGN spec7_wr_ref_top.bmm [current_design]
    # ---------------------------------------------------------------------------
    # -- SPI interface to on board DACs
    # ---------------------------------------------------------------------------
    ......
    hdl/top/spec7_ref_design/spec7_wr_hpsec_top_v2.xdc
    View file @ eea1d0c2
    ......@@ -59,9 +59,6 @@ set_multicycle_path 1 -hold -from [get_clocks clk_125m_gtx_odiv2] -to [get_clock
    set_multicycle_path 3 -setup -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_125m_gtx_odiv2]
    set_multicycle_path 2 -hold -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_125m_gtx_odiv2]
    # Set BMM_INFO_DESIGN property to avoid ERROR during "Write Bitstream"
    set_property BMM_INFO_DESIGN spec7_wr_ref_top.bmm [current_design]
    # ---------------------------------------------------------------------------
    # -- SPI interface to on board DACs
    # ---------------------------------------------------------------------------
    ......
    hdl/top/spec7_ref_design/spec7_wr_ref_top.xdc
    View file @ eea1d0c2
    ......@@ -59,9 +59,6 @@ set_multicycle_path 1 -hold -from [get_clocks clk_125m_gtx_odiv2] -to [get_clock
    set_multicycle_path 3 -setup -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_125m_gtx_odiv2]
    set_multicycle_path 2 -hold -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_125m_gtx_odiv2]
    # Set BMM_INFO_DESIGN property to avoid ERROR during "Write Bitstream"
    set_property BMM_INFO_DESIGN spec7_wr_ref_top.bmm [current_design]
    # ---------------------------------------------------------------------------
    # -- SPI interface to on board DACs
    # ---------------------------------------------------------------------------
    ......
    hdl/top/spec7_ref_design/spec7_wr_ref_top_v2.xdc
    View file @ eea1d0c2
    ......@@ -59,9 +59,6 @@ set_multicycle_path 1 -hold -from [get_clocks clk_125m_gtx_odiv2] -to [get_clock
    set_multicycle_path 3 -setup -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_125m_gtx_odiv2]
    set_multicycle_path 2 -hold -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_125m_gtx_odiv2]
    # Set BMM_INFO_DESIGN property to avoid ERROR during "Write Bitstream"
    set_property BMM_INFO_DESIGN spec7_wr_ref_top.bmm [current_design]
    # ---------------------------------------------------------------------------
    # -- SPI interface to on board DACs
    # ---------------------------------------------------------------------------
    ......
    hdl/top/spec7_tandem_boot/spec7_tandem_boot_top.xdc
    View file @ eea1d0c2
    ......@@ -2,9 +2,6 @@
    # -- Clocks/resets
    # ---------------------------------------------------------------------------
    # Set BMM_INFO_DESIGN property to avoid ERROR during "Write Bitstream"
    #set_property BMM_INFO_DESIGN spec7_wr_ref_top.bmm [current_design]
    # ---------------------------------------------------------------------------
    # -- PCIe
    # ---------------------------------------------------------------------------
    ......
    sw/scripts/viv_do_all.tcl
    View file @ eea1d0c2
    ......@@ -135,7 +135,7 @@ foreach line $content {
    set use_bmm true
    set bmm_file [pwd]/$line
    set bmm_bd ${proj_name}_bd.bmm
    add_files -norecurse $bmm_file
    #add_files -norecurse $bmm_file
    }
    }
    ......
    sw/scripts/viv_generate_bd_bmm.tcl
    View file @ eea1d0c2
    ......@@ -5,7 +5,7 @@
    # Author : Peter Jansweijer <peterj@nikhef.nl>
    # Company : Nikhef
    # Created : 2018-01-24
    # Last update: 2021-06-01
    # Last update: 2022-03-22
    # Platform : FPGA-generics
    # Standard : VHDL
    #-----------------------------------------------------------------------------
    ......@@ -35,10 +35,8 @@
    #-----------------------------------------------------------------------------
    #open_run impl_2
    set project_bmm_files [get_files *.bmm]
    set BB FALSE
    # foreach fn $project_bmm_files {
    # set temp [file rootname $fn]
    # set bd_fn ${temp}_bd.bmm
    ......
    sw/scripts/viv_generate_bd_mmi.tcl
    View file @ eea1d0c2
    ......@@ -5,7 +5,7 @@
    # Author : Peter Jansweijer <peterj@nikhef.nl>
    # Company : Nikhef
    # Created : 2018-01-24
    # Last update: 2021-06-01
    # Last update: 2022-03-22
    # Platform : FPGA-generics
    # Standard : VHDL
    #-----------------------------------------------------------------------------
    ......@@ -34,7 +34,6 @@
    #
    #-----------------------------------------------------------------------------
    set project_bmm_files [get_files *.bmm]
    set BB FALSE
    set mmi_file ${proj_name}.mmi
    ......
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