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SPEC7
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SPEC7
Commits
e50dfa58
Commit
e50dfa58
authored
Apr 12, 2022
by
Peter Jansweijer
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Plain Diff
add generic g_dac_bits (default 16)
parent
fa7e5d55
Pipeline
#3581
failed with stage
in 5 seconds
Changes
4
Pipelines
1
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4 changed files
with
12 additions
and
10 deletions
+12
-10
wr_spec7_pkg.vhd
hdl/board/wr_spec7_pkg.vhd
+1
-1
wrc_board_spec7.vhd
hdl/board/wrc_board_spec7.vhd
+1
-1
xwrc_board_spec7.vhd
hdl/board/xwrc_board_spec7.vhd
+9
-7
wr-cores
hdl/wr-cores
+1
-1
No files found.
hdl/board/wr_spec7_pkg.vhd
View file @
e50dfa58
...
...
@@ -134,7 +134,7 @@ package wr_spec7_pkg is
wrs_rx_cfg_i
:
in
t_rx_streamer_cfg
:
=
c_rx_streamer_cfg_default
;
aux_diag_i
:
in
t_generic_word_array
(
g_diag_ro_size
-1
downto
0
)
:
=
(
others
=>
(
others
=>
'0'
));
aux_diag_o
:
out
t_generic_word_array
(
g_diag_rw_size
-1
downto
0
);
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_value_o
:
out
std_logic_vector
(
31
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
...
...
hdl/board/wrc_board_spec7.vhd
View file @
e50dfa58
...
...
@@ -262,7 +262,7 @@ entity wrc_board_spec7 is
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_value_o
:
out
std_logic_vector
(
31
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
...
...
hdl/board/xwrc_board_spec7.vhd
View file @
e50dfa58
...
...
@@ -78,7 +78,7 @@ entity xwrc_board_spec7 is
g_diag_ro_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
;
g_dac_bits
:
integer
:
=
16
;
g_refclk_tune_pos_slope
:
boolean
:
=
TRUE
;
g_refclk_tune_pos_slope
:
boolean
:
=
TRUE
);
port
(
---------------------------------------------------------------------------
...
...
@@ -228,7 +228,7 @@ entity xwrc_board_spec7 is
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_value_o
:
out
std_logic_vector
(
31
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
tm_clk_aux_lock_en_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
tm_clk_aux_locked_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
...
...
@@ -309,9 +309,9 @@ architecture struct of xwrc_board_spec7 is
-- PLL DACs
signal
dac_dmtd_load
:
std_logic
;
signal
dac_dmtd_data
:
std_logic_vector
(
15
downto
0
);
signal
dac_dmtd_data
:
std_logic_vector
(
g_dac_bits
-1
downto
0
);
signal
dac_refclk_load
:
std_logic
;
signal
dac_refclk_data
:
std_logic_vector
(
15
downto
0
);
signal
dac_refclk_data
:
std_logic_vector
(
g_dac_bits
-1
downto
0
);
signal
sit5359_scl_pad_oen
,
sit5359_sda_pad_oen
:
std_logic
;
signal
sit5359_scl_pad_in
,
sit5359_sda_pad_in
:
std_logic
;
...
...
@@ -613,7 +613,7 @@ begin -- architecture struct
port
map
(
clk_i
=>
clk_sys_62m5
,
rst_n_i
=>
rst_62m5_n
,
value_i
=>
dac_dmtd_data
,
value_i
=>
dac_dmtd_data
(
g_dac_bits
-1
downto
g_dac_bits
-16
)
,
cs_sel_i
=>
"1"
,
load_i
=>
dac_dmtd_load
,
sclk_divsel_i
=>
"001"
,
...
...
@@ -635,7 +635,8 @@ begin -- architecture struct
cmp_sit5359_wr_interface
:
entity
work
.
xwr_sit5359_interface
generic
map
(
g_simulation
=>
g_simulation
)
g_simulation
=>
g_simulation
,
g_dac_bits
=>
g_dac_bits
)
port
map
(
clk_sys_i
=>
clk_sys_62m5
,
rst_n_i
=>
rst_62m5_n
,
...
...
@@ -663,7 +664,7 @@ begin -- architecture struct
port
map
(
clk_i
=>
clk_sys_62m5
,
rst_n_i
=>
rst_62m5_n
,
value_i
=>
dac_refclk_data_slp
,
value_i
=>
dac_refclk_data_slp
(
g_dac_bits
-1
downto
g_dac_bits
-16
)
,
cs_sel_i
=>
"1"
,
load_i
=>
dac_refclk_load
,
sclk_divsel_i
=>
"001"
,
...
...
@@ -699,6 +700,7 @@ begin -- architecture struct
g_diag_ver
=>
g_diag_ver
,
g_diag_ro_size
=>
g_diag_ro_size
,
g_diag_rw_size
=>
g_diag_rw_size
,
g_dac_bits
=>
g_dac_bits
,
g_streamers_op_mode
=>
g_streamers_op_mode
,
g_tx_streamer_params
=>
g_tx_streamer_params
,
g_rx_streamer_params
=>
g_rx_streamer_params
,
...
...
wr-cores
@
8f838645
Subproject commit
e621505c33305c2a128de6f2a46e3aa72833c3c3
Subproject commit
8f83864567d594743b213e9548679aa1939ca842
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