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SPEC7
Commit e29d10b3 authored by Peter Jansweijer's avatar Peter Jansweijer
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Test a sit5359 at 124.992 MHz connected to the clk_125m_dmtd via BullsEye B9/B10

parent beda5e56
Pipeline #3757 failed with stage
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    hdl/board/xwrc_board_spec7.vhd
    View file @ e29d10b3
    ......@@ -625,8 +625,8 @@ begin -- architecture struct
    port map (
    clk_sys_i => clk_sys_62m5,
    rst_n_i => rst_62m5_n,
    tm_dac_value_i => dac_refclk_data,
    tm_dac_value_wr_i => dac_refclk_load,
    tm_dac_value_i => dac_dmtd_data,
    tm_dac_value_wr_i => dac_dmtd_load,
    scl_pad_oen_o => sit5359_scl_pad_oen,
    sda_pad_oen_o => sit5359_sda_pad_oen,
    scl_pad_i => sit5359_scl_pad_in,
    ......
    hdl/syn/spec7_ref_design/proj_properties.tcl
    View file @ e29d10b3
    ......@@ -11,8 +11,8 @@
    set version ""
    # Reference Design (using fmc-dio-5chttla => https://ohwr.org/project/fmc-dio-5chttla/wikis/home)
    # HPSEC Design (using Bulls-Eye connector)
    #set spec7_design spec7_ref_top
    set spec7_design spec7_hpsec_top
    set spec7_design spec7_ref_top
    #set spec7_design spec7_hpsec_top
    # Uncomment the line below for older SPEC7v2
    set version "_v2"
    # ====================================================
    ......
    hdl/top/spec7_ref_design/spec7_wr_ref_top_v2.xdc
    View file @ e29d10b3
    ......@@ -11,9 +11,9 @@ set_property PACKAGE_PIN U5 [get_ports clk_125m_gtx_n_i]
    #set_property PACKAGE_PIN W5 [get_ports clk_125m_gtx_n_i]
    # Bank 35 (HP) VCCO - 1.8 V -- 124.992 MHz DMTD clock
    set_property PACKAGE_PIN D15 [get_ports clk_125m_dmtd_p_i]
    set_property PACKAGE_PIN J14 [get_ports clk_125m_dmtd_p_i]
    set_property IOSTANDARD LVDS [get_ports clk_125m_dmtd_p_i]
    set_property PACKAGE_PIN D14 [get_ports clk_125m_dmtd_n_i]
    set_property PACKAGE_PIN H14 [get_ports clk_125m_dmtd_n_i]
    set_property IOSTANDARD LVDS [get_ports clk_125m_dmtd_n_i]
    create_clock -period 8.000 -name clk_125m_gtx -waveform {0.000 4.000} [get_ports clk_125m_gtx_p_i]
    ......
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