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S
SPEC7
Commit de4a4161 authored by Peter Jansweijer's avatar Peter Jansweijer
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100MHzInTheLoop uses LTC2641 SPI DAC that clocks data on positive clock edge

parent e5ba1214
Pipeline #3707 failed with stage
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    hdl/board/xwrc_board_spec7.vhd
    View file @ de4a4161
    ......@@ -596,7 +596,7 @@ begin -- architecture struct
    g_num_data_bits => 16,
    g_num_extra_bits => 8,
    g_num_cs_select => 1,
    g_sclk_polarity => 0)
    g_sclk_polarity => 1)
    port map (
    clk_i => clk_sys_62m5,
    rst_n_i => rst_62m5_n,
    ......@@ -625,7 +625,7 @@ begin -- architecture struct
    g_num_data_bits => 16,
    g_num_extra_bits => 8,
    g_num_cs_select => 1,
    g_sclk_polarity => 0)
    g_sclk_polarity => 1)
    port map (
    clk_i => clk_sys_62m5,
    rst_n_i => rst_62m5_n,
    ......
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