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SPEC7
Commit ca3fae43 authored by Peter Jansweijer's avatar Peter Jansweijer
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Prepare for 100 MHz output

parent fdead304
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    hdl/sim/spec7_ref_design/VCom_spec7_wr_ref_top_Functional.tcl
    View file @ ca3fae43
    ......@@ -65,7 +65,7 @@ vcom -explicit -93 -work work ../../wr-cores/modules/wr_streamers/wr_streamers_w
    vcom -explicit -93 -work work ../../wr-cores/modules/wrc_core/wrc_diags_wb.vhd
    vcom -explicit -93 -work work ../../wr-cores/modules/wrc_core/wrc_syscon_wb.vhd
    vcom -explicit -93 -work work ../../board/even_odd_det.vhd
    vcom -explicit -93 -work work ../../top/spec7_ref_design/gen_10mhz.vhd
    vcom -explicit -93 -work work ../../top/spec7_ref_design/gen_x_mhz.vhd
    vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd
    vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
    vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd
    ......
    hdl/syn/spec7_ref_design/proj_file_list.txt
    View file @ ca3fae43
    ......@@ -66,7 +66,7 @@
    ../../wr-cores/modules/wrc_core/wrc_diags_wb.vhd
    ../../wr-cores/modules/wrc_core/wrc_syscon_wb.vhd
    ../../board/even_odd_det.vhd
    ../../top/spec7_ref_design/gen_10mhz.vhd
    ../../top/spec7_ref_design/gen_x_mhz.vhd
    ../../wr-cores/ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd
    ../../wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
    ../../wr-cores/ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd
    ......
    hdl/top/spec7_ref_design/gen_10mhz.vhd → hdl/top/spec7_ref_design/gen_x_mhz.vhd
    View file @ ca3fae43
    ......@@ -47,16 +47,19 @@ library work;
    use work.gencores_pkg.all;
    use work.genram_pkg.all;
    entity gen_10mhz is
    entity gen_x_mhz is
    generic (
    g_divide : integer := 50
    );
    port (
    clk_500m_i : in std_logic;
    rst_n_i : in std_logic;
    pps_i : in std_logic;
    -- generated 10 MHz synced with PPS
    clk_10mhz_o : out std_logic := '0');
    end gen_10mhz;
    clk_x_mhz_o : out std_logic := '0');
    end gen_x_mhz;
    architecture rtl of gen_10mhz is
    architecture rtl of gen_x_mhz is
    signal rst_n_synced : std_logic := '0';
    signal pps_synced : std_logic := '0';
    ......@@ -75,24 +78,27 @@ begin -- rtl
    end if;
    end process;
    pr_10mhz_gen : process (clk_500m_i, rst_n_synced)
    variable cntr: integer range 0 to 99;
    pr_x_mhz_gen : process (clk_500m_i, rst_n_synced)
    variable cntr: integer range 0 to g_divide - 1;
    begin -- process pr_10mhz_gen
    if rst_n_synced = '0' then
    cntr := 0;
    elsif rising_edge(clk_500m_i) then
    if ((pps_synced = '1' and pps_delayed = '0') or cntr = 49) then
    if cntr < g_divide / 2 then
    clk_x_mhz_o <= '1';
    else
    clk_x_mhz_o <= '0';
    end if;
    if ((pps_synced = '1' and pps_delayed = '0') or cntr = g_divide - 1) then
    cntr := 0;
    elsif cntr < 49 then
    elsif cntr < g_divide - 1 then
    cntr := cntr + 1;
    end if;
    if cntr < 25 then
    clk_10mhz_o <= '1';
    else
    clk_10mhz_o <= '0';
    end if;
    end if;
    end process pr_10mhz_gen;
    end process pr_x_mhz_gen;
    end rtl;
    hdl/top/spec7_ref_design/spec7_wr_ref_top.vhd
    View file @ ca3fae43
    ......@@ -377,6 +377,7 @@ architecture top of spec7_wr_ref_top is
    signal clk_ref_62m5 : std_logic;
    signal clk_ref_div2 : std_logic;
    signal clk_10m_out : std_logic;
    signal clk_100m_out : std_logic;
    signal clk_500m : std_logic;
    signal clk_ext_10m : std_logic;
    ......@@ -427,14 +428,17 @@ architecture top of spec7_wr_ref_top is
    );
    end component pll_62m5_500m;
    component gen_10mhz is
    component gen_x_mhz is
    generic (
    g_divide : integer
    );
    port (
    clk_500m_i : in std_logic;
    clk_500m_i : in std_logic;
    rst_n_i : in std_logic;
    pps_i : in std_logic;
    clk_10mhz_o : out std_logic
    clk_x_mhz_o : out std_logic
    );
    end component gen_10mhz;
    end component gen_x_mhz;
    begin -- architecture top
    ......@@ -700,10 +704,11 @@ end generate gen_irig_b;
    end process;
    ------------------------------------------------------------------------------
    -- 10MHz output generation
    -- 10MHz / 100MHz output generation
    ------------------------------------------------------------------------------
    -- A 500 MHz reference clock is necessary since 10 MHz = 50 ns '1', 50 ns '0'
    -- and 50 ns is divisible by 2 ns (not by 8 or 4 ns!) hence 500 MHz.
    -- A 500 MHz reference clock is necessary since:
    -- 10 MHz = 50 ns '1', 50 ns '0' (25 ticks '1', 25 ticks '0', duty cycle 50%)
    -- 100 MHz = 5 ns '1', 5 ns '0' (4 ticks '1' , 6 ticks '0', duty cycle 40%)
    cmp_pll_62m5_500m: pll_62m5_500m
    port map (
    areset_n_i => rst_ref_62m5_n,
    ......@@ -712,12 +717,15 @@ end generate gen_irig_b;
    pll_500m_locked_o => open
    );
    cmp_gen_10mhz: gen_10mhz
    cmp_gen_10mhz: gen_x_mhz
    generic map (
    g_divide => 50
    )
    port map (
    clk_500m_i => clk_500m,
    rst_n_i => rst_ref_62m5_n,
    pps_i => wrc_pps_out,
    clk_10mhz_o => clk_10m_out
    clk_x_mhz_o => clk_10m_out
    );
    cmp_obuf_be_10mhz_out : OBUFDS
    ......@@ -726,6 +734,18 @@ end generate gen_irig_b;
    O => be_clk_10m_p_o,
    OB => be_clk_10m_n_o);
    cmp_gen_100mhz: gen_x_mhz
    generic map (
    g_divide => 5
    )
    port map (
    clk_500m_i => clk_500m,
    rst_n_i => rst_ref_62m5_n,
    pps_i => wrc_pps_out,
    clk_x_mhz_o => clk_100m_out
    );
    -- For the time being, 100 MHz is output is not used
    ------------------------------------------------------------------------------
    -- LEDs
    ------------------------------------------------------------------------------
    ......
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