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SPEC7
Commit a612dd92 authored by Peter Jansweijer's avatar Peter Jansweijer
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Adjust .gitlab-ci.yml to new directory structure, viv_do_all leaves .bit, .mmi… 

Adjust .gitlab-ci.yml to new directory structure, viv_do_all leaves .bit, .mmi and .log files in directory work
parent 07ad4910
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    Showing with 19 additions and 12 deletions
    .gitlab-ci.yml
    View file @ a612dd92
    ......@@ -12,20 +12,23 @@ SPEC7_REF_DESIGN build:
    script:
    - /entrypoint.sh
    - source ~/setup_vivado.sh
    - git checkout spec7_golden
    - git checkout proposed_master
    - git submodule init && git submodule update
    - cd hdl/wr-cores && git submodule init && git submodule update
    - cd ../../hdl/spec7_ref_design/syn
    - cd ../../hdl/syn/spec7_ref_design
    - source /opt/Xilinx/Vivado/2019.2/settings64.sh
    - vivado -mode tcl -source ../../../sw/scripts/viv_do_all.tcl
    artifacts:
    when: always
    paths:
    - hdl/spec7_ref_design/syn/work/spec7_wr_ref_top.runs/impl_1/*.bit
    - hdl/spec7_ref_design/syn/work/spec7_wr_ref_top.runs/impl_1/*.rpt
    - hdl/spec7_ref_design/syn/work/spec7_wr_ref_top.runs/impl_1/*.csv
    - dl/spec7_ref_design/syn/work/spec7_wr_ref_top.runs/synth_1/*.rpt
    - hdl/spec7_ref_design/syn/work/spec7_wr_ref_top.runs/processing_system_pcie_xdma_0_0_synth_1/*.rpt
    - hdl/spec7_ref_design/syn/work/spec7_wr_ref_top.runs/processing_system_pcie_processing_system7_0_0_synth_1/*.rpt
    - hdl/spec7_ref_design/syn/work/spec7_wr_ref_top.runs/processing_system_pcie_smartconnect_0_0_synth_1/*.rpt
    - hdl/syn/spec7_ref_design/work/spec7_wr_ref_top.runs/impl_1/*.bit
    - hdl/syn/spec7_ref_design/work/spec7_wr_ref_top.runs/impl_1/*.rpt
    - hdl/syn/spec7_ref_design/work/spec7_wr_ref_top.runs/impl_1/*.csv
    - hdl/syn/spec7_ref_design/work/spec7_wr_ref_top.runs/synth_1/*.rpt
    - hdl/syn/spec7_ref_design/work/spec7_wr_ref_top.runs/processing_system_pcie_xdma_0_0_synth_1/*.rpt
    - hdl/syn/spec7_ref_design/work/spec7_wr_ref_top.runs/processing_system_pcie_processing_system7_0_0_synth_1/*.rpt
    - hdl/syn/spec7_ref_design/work/spec7_wr_ref_top.runs/processing_system_pcie_smartconnect_0_0_synth_1/*.rpt
    - hdl/syn/spec7_ref_design/work/*.bit
    - hdl/syn/spec7_ref_design/work/*.mmi
    - hdl/syn/spec7_ref_design/work/*.log
    sw/scripts/viv_do_all.tcl
    View file @ a612dd92
    ......@@ -167,11 +167,16 @@ if {$use_bmm} {
    close_design
    # Generate a new name for .bit and .mmi file and copy to project directory.
    # Also create a copy of these files in the work directory that can be picked up by .gitlab-ci.yml
    # Create a senible name including date and time
    set bitfile_name ${spec7_design}_[string range $device 3 6]_[clock format [clock seconds] -format %y%m%d_%H%M]
    file copy ./work/${proj_name}.runs/impl_1/${proj_name}.bit ../${bitfile_name}.bit
    file copy ./work/${proj_name}.runs/impl_1/${proj_name}.bit ./work/${bitfile_name}.bit
    if [file exists ./${proj_name}.mmi] {
    file copy ./${proj_name}.mmi ../${bitfile_name}.mmi
    file copy ./${proj_name}.mmi ../${bitfile_name}.mmi
    file copy ./${proj_name}.mmi ./work/${bitfile_name}.mmi
    exec updatemem -meminfo ./${proj_name}.mmi -data ${lm32_wrpc_elf} -bit ./work/${proj_name}.runs/impl_1/${proj_name}.bit -proc ${lm32_wrpc_instpath} -out ../${bitfile_name}_elf.bit -force
    file copy ../${bitfile_name}_elf.bit ./work/${bitfile_name}_elf.bit
    }
    set syn_dir [pwd]
    ......@@ -193,5 +198,4 @@ puts $git_log_fp "spec7.git $spec7_sha"
    puts $git_log_fp "wr-cores.git $wr_cores_sha"
    puts $git_log_fp "general-cores.git $general_cores_sha"
    close $git_log_fp
    exec updatemem -meminfo ./${proj_name}.mmi -data ${lm32_wrpc_elf} -bit ./work/${proj_name}.runs/impl_1/${proj_name}.bit -proc ${lm32_wrpc_instpath} -out ../${bitfile_name}_elf.bit -force
    file copy ../${bitfile_name}.log ./work/${bitfile_name}.log
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