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SPEC7
Commit 95bddac1 authored by Peter Jansweijer's avatar Peter Jansweijer
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Virgo demonstrator used be_abscal_txts signals to output 100 MHz. 

Reset front button resets spec7 (via fmc_la27_p).
parent eea1d0c2
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    hdl/sim/spec7_ref_design/test.tcl
    View file @ 95bddac1
    force /spec7_wr_ref_top/reset_n_i 0,1 200 ns
    force /spec7_wr_ref_top/fmc_la27_p 1
    force /spec7_wr_ref_top/uart_rxd_i 0
    ......
    hdl/top/spec7_ref_design/spec7_wr_hpsec_top.xdc
    View file @ 95bddac1
    ......@@ -582,6 +582,8 @@ set_property IOSTANDARD LVCMOS25 [get_ports fmc_la26_n]
    # Bank 13 VCCO - 2.5 V FMC_XM105 J20 pin 14
    set_property PACKAGE_PIN AC18 [get_ports fmc_la27_p]
    set_property IOSTANDARD LVCMOS25 [get_ports fmc_la27_p]
    # Virgo demonstrator reset front button
    set_property PULLUP TRUE [get_ports fmc_la27_p]
    #set_property DIFF_TERM TRUE [get_ports fmc_la27_p]
    # Bank 13 VCCO - 2.5 V FMC_XM105 J20 pin 16
    set_property PACKAGE_PIN AC19 [get_ports fmc_la27_n]
    ......
    hdl/top/spec7_ref_design/spec7_wr_hpsec_top_v2.xdc
    View file @ 95bddac1
    ......@@ -582,6 +582,8 @@ set_property IOSTANDARD LVCMOS25 [get_ports fmc_la26_n]
    # Bank 13 VCCO - 2.5 V FMC_XM105 J20 pin 14
    set_property PACKAGE_PIN AC18 [get_ports fmc_la27_p]
    set_property IOSTANDARD LVCMOS25 [get_ports fmc_la27_p]
    # Virgo demonstrator reset front button
    set_property PULLUP TRUE [get_ports fmc_la27_p]
    #set_property DIFF_TERM TRUE [get_ports fmc_la27_p]
    # Bank 13 VCCO - 2.5 V FMC_XM105 J20 pin 16
    set_property PACKAGE_PIN AC19 [get_ports fmc_la27_n]
    ......
    hdl/top/spec7_ref_design/spec7_wr_ref_top.vhd
    View file @ 95bddac1
    ......@@ -380,6 +380,7 @@ architecture top of spec7_wr_ref_top is
    signal clk_100m_out : std_logic;
    signal clk_500m : std_logic;
    signal clk_ext_10m : std_logic;
    signal rst_n_int : std_logic;
    -- DAC signals for reference clock
    signal dac_refclk_sclk_int_o : std_logic;
    ......@@ -442,6 +443,10 @@ architecture top of spec7_wr_ref_top is
    begin -- architecture top
    -- Virgo demonstartor reset front button (Timing Main Board J3) connects
    -- via FMC Breakour Extended to fmc_la27_p.
    rst_n_int <= '0' when reset_n_i = '0' or fmc_la27_p = '0' else '1';
    -- Never trigger PS_POR or PROGRAM_B
    suicide_n_o <= '1';
    wdog_n_o <= '1';
    ......@@ -536,7 +541,7 @@ Pcie: ps_pcie_wrapper
    AXI2WB : xwb_axi4lite_bridge
    port map(
    clk_sys_i => clk_sys_62m5,
    rst_n_i => reset_n_i,
    rst_n_i => rst_n_int,
    axi4_slave_i => m_axil_o,
    axi4_slave_o => m_axil_i,
    ......@@ -554,7 +559,7 @@ gen_irig_b : if (g_irig_b_enable = TRUE) generate
    )
    port map(
    clk_i => clk_sys_62m5,
    rst_n_i => reset_n_i,
    rst_n_i => rst_n_int,
    pps_i => wrc_pps_out,
    irig_b_o => irigb,
    tm_time_valid_i => tm_time_valid,
    ......@@ -582,7 +587,7 @@ end generate gen_irig_b;
    g_refclk_tune_pos_slope => g_refclk_tune_pos_slope
    )
    port map (
    areset_n_i => reset_n_i,
    areset_n_i => rst_n_int,
    clk_125m_dmtd_n_i => clk_125m_dmtd_n_i,
    clk_125m_dmtd_p_i => clk_125m_dmtd_p_i,
    clk_125m_gtx_n_i => clk_125m_gtx_n_i,
    ......@@ -683,9 +688,13 @@ end generate gen_irig_b;
    -- B09, B10 NC
    -- B11, B12 PPS_IN single ended, NC (Bank 13 AE23, )
    ----------------------------------------------------------------------------------------------------------
    -- Vrigo Demonstrator uses be_abscal_txts signals to forward phase aligned 100MHz to the Timing Main Board
    ----------------------------------------------------------------------------------------------------------
    cmp_obuf_be_abscal_txts : OBUFDS
    port map (
    I => wrc_abscal_txts_out,
    -- I => wrc_abscal_txts_out,
    I => clk_100m_out,
    O => be_abscal_txts_p_o,
    OB => be_abscal_txts_n_o);
    ......@@ -719,7 +728,7 @@ end generate gen_irig_b;
    cmp_gen_10mhz: gen_x_mhz
    generic map (
    g_divide => 50
    g_divide => 50 -- 500/50 MHz = 10 MHz (50% duty cycle)
    )
    port map (
    clk_500m_i => clk_500m,
    ......@@ -736,7 +745,7 @@ end generate gen_irig_b;
    cmp_gen_100mhz: gen_x_mhz
    generic map (
    g_divide => 5
    g_divide => 5 -- 500/5 MHz = 100 MHz (40% duty cycle!)
    )
    port map (
    clk_500m_i => clk_500m,
    ......@@ -744,7 +753,6 @@ end generate gen_irig_b;
    pps_i => wrc_pps_out,
    clk_x_mhz_o => clk_100m_out
    );
    -- For the time being, 100 MHz is output is not used
    ------------------------------------------------------------------------------
    -- LEDs
    ......
    hdl/top/spec7_ref_design/spec7_wr_ref_top.xdc
    View file @ 95bddac1
    ......@@ -577,6 +577,8 @@ set_property IOSTANDARD LVCMOS25 [get_ports fmc_la26_n]
    # Bank 13 VCCO - 2.5 V FMC_XM105 J20 pin 14
    set_property PACKAGE_PIN AC18 [get_ports fmc_la27_p]
    set_property IOSTANDARD LVCMOS25 [get_ports fmc_la27_p]
    # Virgo demonstrator reset front button
    set_property PULLUP TRUE [get_ports fmc_la27_p]
    #set_property DIFF_TERM TRUE [get_ports fmc_la27_p]
    # Bank 13 VCCO - 2.5 V FMC_XM105 J20 pin 16
    set_property PACKAGE_PIN AC19 [get_ports fmc_la27_n]
    ......
    hdl/top/spec7_ref_design/spec7_wr_ref_top_v2.xdc
    View file @ 95bddac1
    ......@@ -577,6 +577,8 @@ set_property IOSTANDARD LVCMOS25 [get_ports fmc_la26_n]
    # Bank 13 VCCO - 2.5 V FMC_XM105 J20 pin 14
    set_property PACKAGE_PIN AC18 [get_ports fmc_la27_p]
    set_property IOSTANDARD LVCMOS25 [get_ports fmc_la27_p]
    # Virgo demonstrator reset front button
    set_property PULLUP TRUE [get_ports fmc_la27_p]
    #set_property DIFF_TERM TRUE [get_ports fmc_la27_p]
    # Bank 13 VCCO - 2.5 V FMC_XM105 J20 pin 16
    set_property PACKAGE_PIN AC19 [get_ports fmc_la27_n]
    ......
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